MAX1270BCAI Datasheet, PDF (6/20 Pages) Maxim Integrated Products – Multirange, +5V, 8-Channel, Serial 12-Bit ADCs

Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
TIMING CHARACTERISTICS
(V_DD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, V_REF = +4.096V; 4.7µF at REF; external clock; f_CLK =
2.0MHz (MAX127_B); f_CLK = 1.8MHz (MAX127_A); T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are T_A = +25°C.)
(Figures 2, 5, 7, 10)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DIN to SCLK Setup
t_DS
100
ns
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse-Width High
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSH
t_CH
C_LOAD = 100pF
C_LOAD = 100pF
0
ns
20
170
ns
120
ns
100
ns
100
ns
0
ns
200
ns
SCLK Pulse-Width Low
SCLK Fall to SSTRB
CS to SSTRB Output Enable
CS to SSTRB Output Disable
t_CL
200
t_SSTRB C_LOAD = 100pF
t_SDV C_LOAD = 100pF, external clock mode only
t_STR C_LOAD = 100pF, external clock mode only
ns
200
ns
200
ns
200
ns
SSTRB Rise to SCLK Rise
t_SCK Internal clock mode only (Note 4)
0
ns
Note 1: Accuracy specifications tested at V_DD = +5.0V. Performance at power-supply tolerance limit is guaranteed by power-supply
rejection test.
Note 2: External reference: V_REF = 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2 LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels. V_IN = ±5V (MAX1270), V_IN = ±4V (MAX1271).
Note 4: Guaranteed by design, not production tested.
Note 5: Use static external loads during conversion for specified accuracy.
Note 6: Tested using internal reference.
Note 7: PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.
Note 8: Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).
Note 9: Not production tested. Provided for design guidance only.
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