MAX11108 Datasheet, PDF (9/16 Pages) Maxim Integrated Products – Single-Ended Analog Input 12-Bit Resolution ADC

MAX11108
Tiny, 2.1mm x 1.6mm, 3Msps,
Low-Power, Serial 12-Bit ADC
Typical Operating Circuit
VDD
V_OVDD
+3V
+3V
REF
REFERENCE INPUT
+3V
MAX11108
SCLK
DOUT
CS
ANALOG
AIN
INPUT
AGND
SCK
MISO
CPU
SS
Detailed Description
The MAX11108 is a tiny, fast, 12-bit, low-power, single-
supply ADC. This device “communicates” from 1.5V to
V_DD, operates from a 2.2V to 3.6V supply, and consumes
only 9mW (V_DD = 3V)/6.6mW (V_DD = 2.2V) at 3Msps.
This 3Msps device is capable of sampling at full rate when
driven by a 48MHz clock.
The conversion result appears at DOUT, MSB first, with a
leading zero followed by the 12-bit result. A 12-bit result is
followed by two trailing zeros (see Figure 1).
The device features a dedicated reference input (REF).
The input signal range for AIN is defined as 0V to V_REF
with respect to AGND.
This ADC includes a power-down feature allowing
minimized power consumption at 2.5µA/ksps for lower
throughput rates. The wake-up and power-down feature is
controlled by using the SPI interface as described in the
Operating Modes section.
Serial Interface
This device features a 3-wire serial interface that directly
connects to SPI/QSPI/MICROWIRE devices without
external logic. Figure 1 shows the interface signals for
a single conversion frame to achieve maximum through-
put.
The falling edge of CS defines the sampling instant.
Once CS transitions low, the external clock signal
(SCLK) controls the conversion.
The SAR core successively extracts binary-weighted
bits in every clock cycle. The MSB appears on the data
bus during the 2nd clock cycle with a delay outlined in
the timing specifications. All extracted data bits appear
successively on the data bus with the LSB appearing
during the 13th clock cycle for 12-bit operation. The
serial data stream of conversion bits is preceded by a
leading “zero” and succeeded by trailing “zeros.” The data
output (DOUT) goes into high-impedance state during the
16th clock cycle.
To sustain the maximum sample rate, the device has to
be resampled immediately after the 16th clock cycle. For
lower sample rates, the CS falling edge can be delayed
leaving DOUT in a high-impedance condition. Pull CS
high after the 10th SCLK falling edge (see the Operating
Modes section).
Analog Input
The ADC produces a digital output that corresponds to the
analog input voltage within the specified operating range
of 0 to VREF.
Figure 5 shows an equivalent circuit for the analog input
AIN. Internal protection diodes D1/D2 confine the analog
input voltage within the power rails (V_DD, AGND). The
analog input voltage can swing from (AGND - 0.3V) to
(V_DD + 0.3V) without damaging the device.
The electric load presented to the external stage driv-
ing the analog input varies depending on which mode
the ADC is in: track mode vs. conversion mode. In track
mode, the internal sampling capacitor C_S (16pF) has
www.maximintegrated.com
Maxim Integrated │  9