MAX11108 Datasheet, PDF (4/16 Pages) Maxim Integrated Products – Single-Ended Analog Input 12-Bit Resolution ADC

MAX11108
Tiny, 2.1mm x 1.6mm, 3Msps,
Low-Power, Serial 12-Bit ADC
Electrical Characteristics (continued)
(V_DD = 2.2V to 3.6V, V_REF = V_DD, V_OVDD = V_DD. f_SCLK = 48MHz, 50% duty cycle, 3Msps. C_DOUT = 10pF, T_A = -40°C to +125°C,
unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER SUPPLY
Positive Supply Voltage
Digital I/O Supply Voltage
Positive Supply Current
(Full-Power Mode)
V_DD
V_OVDD
I_VDD
I_OVDD
V_AIN = V_GND
V_AIN = V_GND
2.2
3.6
V
1.5
V_DD
V
3.3
mA
0.33
Positive Supply Current (Full-
Power Mode), No Clock
I_VDD
1.98
mA
Power-Down Current
I_PD
Line Rejection
TIMING CHARACTERISTICS (Note 2)
Quiet Time
t_Q
CS Pulse Width
t₁
CS Fall to SCLK Setup
t₂
CS Falling Until DOUT High-
Impedance Disabled
t₃
Leakage only
V_DD = 2.2V to 3.6V, V_REF = 2.2V
(Note 3)
(Note 3)
(Note 3)
(Note 3)
1.3
10
µA
0.7
LSB/V
4
ns
10
ns
5
ns
1
ns
Data Access Time After SCLK
Falling Edge
t₄
Figure 2, V_OVDD = 2.2V to 3.6V
Figure 2, V_OVDD = 1.5V to 2.2V
SCLK Pulse Width Low
t₅
Percentage of clock period (Note 3)
40
SCLK Pulse Width High
t₆
Percentage of clock period (Note 3)
40
Data Hold Time From SCLK
Falling Edge
t₇
Figure 3 (Note 3)
5
15
ns
16.5
60
%
60
%
ns
SCLK Falling Until DOUT High-
Impedance
t₈
Figure 4 (Note 3)
2.5
14
ns
Power-Up Time
Conversion cycle (Note 3)
Note 2: All timing specifications given are with a 10pF capacitor.
Note 3: Guaranteed by design in characterization; not production tested.
1
Cycle
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