MAX11108 Datasheet, PDF (10/16 Pages) Maxim Integrated Products – Single-Ended Analog Input 12-Bit Resolution ADC

MAX11108
Tiny, 2.1mm x 1.6mm, 3Msps,
Low-Power, Serial 12-Bit ADC
to be charged through the resistor R (50Ω) to the input
voltage. For faithful sampling of the input, the capacitor
voltage on C_S has to settle to the required accuracy dur-
ing the track time.
The source impedance of the external driving stage in
conjunction with the sampling switch resistance affects
the settling performance. The THD vs. Input Resistance
graph in the Typical Operating Characteristics shows
THD sensitivity as a function of the signal source imped-
ance. Keep the source impedance at a minimum for high-
dynamic performance applications. Use a high-perfor-
mance op amp such as the MAX4430 to drive the analog
input, thereby decoupling the signal source and the ADC.
While the ADC is in conversion mode, the sampling
switch is open presenting a pin capacitance, C_P
(C_P = 5pF), to the driving stage. See the Applications
Information section for information on choosing an appro-
priate buffer for the ADC.
ADC Transfer Function
The output format is straight binary. The code transi-
tions midway between successive integer LSB values
such as 0.5 LSB, 1.5 LSB, etc. The LSB size is V_REF/2n
where n = 12. The ideal transfer characteristic is shown
in Figure 9.
VDD SWITCH CLOSED IN TRACK MODE
SWITCH OPEN IN CONVERSION MODE
D1
R
CS
AIN
CP
D2
Operating Modes
The IC offers two modes of operation: normal mode and
power-down mode. The logic state of the CS signal dur-
ing a conversion activates these modes. The power-down
mode can be used to optimize power dissipation with
respect to sample rate.
Normal Mode
In normal mode, the device is powered up at all times,
thereby achieving its maximum throughput rates. Figure
6 shows the timing diagram in normal mode. The falling
edge of CS samples the analog input signal, starts a con-
version, and frames the serial data transfer.
To remain in normal mode, keep CS low until the falling
edge of the 10th SCLK cycle. Pulling CS high after the
10th SCLK falling edge keeps the part in normal mode.
However, pulling CS high before the 10th SCLK falling
edge terminates the conversion, DOUT goes into high-
impedance mode, and the device enters power-down
mode. See Figure 7.
Power-Down Mode
In power-down mode, all bias circuitry is shut down draw-
ing typically only 1.3µA of leakage current. To save power,
put the device in power-down mode between conver-
sions. Using the power-down mode between conversions
is ideal for saving power when sampling the analog input
infrequently.
Entering Power-Down Mode
To enter power-down mode, drive CS high between the
2nd and 10th falling edges of SCLK (see Figure 7). By
pulling CS high, the current conversion terminates and
DOUT enters high impedance.
Figure 5. Analog Input Circuit
KEEP CS LOW UNTIL AFTER THE 10TH SCLK FALLING EDGE
PULL CS HIGH AFTER THE 10TH SCLK FALLING EDGE
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
HIGH
IMPEDANCE
Figure 6. Normal Mode
VALID DATA
HIGH
IMPEDANCE
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