MAX11108 Datasheet, PDF (11/16 Pages) Maxim Integrated Products – Single-Ended Analog Input 12-Bit Resolution ADC

MAX11108
Tiny, 2.1mm x 1.6mm, 3Msps,
Low-Power, Serial 12-Bit ADC
PULL CS HIGH AFTER THE 2ND AND BEFORE THE 10TH SCLK FALLING EDGE
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DOUT
HIGH
IMPEDANCE
INVALID
DATA
INVALID DATA OR HIGH IMPEDANCE
Figure 7. Entering Power-Down Mode
HIGH IMPEDANCE
CS
SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DOUT
HIGH
IMPEDANCE
INVALID DATA (DUMMY CONVERSION)
Figure 8. Exiting Power-Down Mode
HIGH
IMPEDANCE
VALID DATA
HIGH
IMPEDANCE
OUTPUT CODE
111...111
111...110
111...101
FS - 1.5 x LSB
000...010
000...001
000...000
0123
0.5 x LSB
2ⁿ-2 2ⁿ-1 2ⁿ
ANALOG
INPUT (LSB)
FULL SCALE (FS):
AIN = V_REF
n = RESOLUTION
Figure 9. ADC Transfer Function
Exiting Power-Down Mode
To exit power-down mode, implement one dummy conver-
sion by driving CS low for at least 10 clock cycles (see
Figure 8). The data on DOUT is invalid during this dummy
conversion. The first conversion following the dummy
cycle contains a valid conversion result.
The power-up time equals the duration of the dummy
cycle, and is dependent on the clock frequency. The pow-
er-up time for 3Msps operation (48MHz SCLK) is 333ns.
Supply Current vs. Sampling Rate
For applications requiring lower throughput rates, the
user can reduce the clock frequency (f_SCLK) to lower the
sample rate. Figure 10 shows the typical supply current
(I_VDD) as a function of sample rate (f_S). The part operates
in normal mode and is never powered down.
The user can also power down the ADC between conver-
sions by using the power-down mode. Figure 11 shows
that as the sample rate is reduced, the device remains in
the power-down state longer and the average supply cur-
rent (I_VDD) drops accordingly.
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