DS4520 Datasheet, PDF (9/10 Pages) Maxim Integrated Products – 9-Bit I2C Nonvolatile I/O Expander Plus Memory

9-Bit I²C Nonvolatile
I/O Expander Plus Memory
If an incorrect slave address is written, the DS4520
assumes the master is communicating with another I²C
device and ignores the communication until the next
start condition is sent.
Memory Address: During an I²C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
I²C Communication
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a start condition,
writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a stop condition.
The DS4520 is capable of writing up to 8 bytes (one
page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte
is sent. The address counter limits the write to one 8-
byte page. Attempts to write to additional pages of
memory without sending a stop condition between
pages results in the address counter wrapping around
to the beginning of the present row. The first row
begins at address 00h and subsequent rows begin at
multiples of 8 there on (08h, 10h, 18h, 20h, etc).
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the page,
and then wait for the bus free or EEPROM write time to
elapse. Then the master can generate a new start con-
dition, write the slave address byte (R/W = 0), and the
first memory address of the next memory row before
continuing to write data.
Acknowledge Polling: Any time an EEPROM page is
written, the DS4520 requires the EEPROM write time
(t_W) after the stop condition to write the contents of the
page to EEPROM. During the EEPROM write time, the
device does not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS4520, which allows communication to continue as
soon as the device is ready. The alternative to acknowl-
edge polling is to wait for a maximum period of t_W to
elapse before attempting to access the device.
EEPROM Write Cycles: When EEPROM writes occur,
the DS4520 writes the whole EEPROM memory page
even if only a single byte on a page was modified.
Writes that do not modify all 8 bytes on the page are
valid and do not corrupt any other bytes on the same
page. Because the whole page is written, even bytes
on the page that were not modified during the transac-
tion are still subject to a write cycle. The DS4520’s
EEPROM write cycles are specified in the Nonvolatile
Memory Characteristics table. The specification shown
is at the worst-case temperature. It is capable of han-
dling approximately 10x that many writes at room tem-
perature.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read oper-
ation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a start condition, writes the slave
address byte with R/W = 1, reads the data byte with a
NACK to indicate the end of the transfer, and generates
a stop condition. However, since requiring the master
to keep track of the memory address counter is imprac-
tical, the following method should be used to perform
reads from a specified memory location.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a start condition, writes the slave address byte
(R/W = 0), writes the memory address where it desires
to read, generates a repeated start condition, writes the
slave address byte (R/W = 1), reads data with ACK or
NACK as applicable, and generates a stop condition.
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