DS4520 Datasheet, PDF (6/10 Pages) Maxim Integrated Products – 9-Bit I2C Nonvolatile I/O Expander Plus Memory

9-Bit I²C Nonvolatile
I/O Expander Plus Memory
Detailed Description
The DS4520 contains nine bidirectional, NV, input/out-
put (I/O) pins, and a 64-byte EEPROM user memory.
The I/O pins and user memory are accessible through
an I²C-compatible serial bus.
Programmable NV I/O Pins
Each programmable I/O pin consists of an input and an
open-collector output with a selectable internal pullup
resistor. To enable the pullups for each I/O pin, write to
the Pullup Enable Registers (F0h and F1h). To pull the
output low or place the pulldown transistor into a high-
impedance state, write to the I/O Control Registers (F2h
and F3h). To read the voltage levels present on the I/O
pins, read the I/O Status Registers (F8h and F9h). To
determine the status of the output register, read the I/O
Control Registers and the Pullup Resistor Registers.
The I/O Control Registers and the Pullup Enable
Registers are all SRAM shadowed EEPROM registers. It
is possible to disable the EEPROM writes of the regis-
ters using the SEE bit in the Configuration Register.
This reduces the time required to write to the register
and increases the amount of times the I/O pins can be
adjusted before the EEPROM is worn out.
Memory Map and Memory Types
The DS4520 memory map is shown in Table 1. Three
different types of memory are present in the DS4520:
EEPROM, SRAM shadowed EEPROM, and SRAM.
Memory locations specified as EEPROM are NV.
Writing to these locations results in an EEPROM write
cycle for a time specified by t_WR in the AC Electrical
Characteristics table. Locations specified as SRAM
shadowed EEPROM can be configured to operate in
one of two modes specified by the SEE bit (the LSB of
the Configuration Register, F4h). When the SEE bit = 0
(default), the memory location acts like EEPROM.
However, when SEE = 1, shadow SRAM is written to
instead of the EEPROM. This eliminates both the
EEPROM write time, t_RW, as well as the concern of
wearing out the EEPROM. This is ideal for applications
that wish to constantly write to the I/Os. Power-up
default states can be programmed for the I/Os in
EEPROM (with SEE = 0) and then once powered-up,
SEE can be written to a 1 so the I/Os can be updated
periodically in SRAM. The final type of memory present
in the DS4520 is standard SRAM.
Slave Address and Address Pins
The DS4520’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure 1.
Address pins connected to GND result in a ‘0’ in the cor-
responding bit position in the slave address. Conversely,
address pins connected to V_CC result in a ‘1’ in the cor-
responding bit positions. I²C communication is
described in detail in a later section.
I²C Serial Interface Description
I²C Definitions
The following terminology is commonly used to
describe I²C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start, and stop conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Start Condition: A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition: A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer
to indicate that it immediately initiates a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start
condition. See the timing diagram for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 2). Data is
shifted into the device during the rising edge of the SCL.
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