DS4520 Datasheet, PDF (8/10 Pages) Maxim Integrated Products – 9-Bit I2C Nonvolatile I/O Expander Plus Memory

9-Bit I²C Nonvolatile
I/O Expander Plus Memory
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time before the next rising edge of SCL during a bit
read (see Figure 2). The device shifts out each bit of
data on SDA at the falling edge of the previous SCL
pulse and the data bit is valid at the rising edge of the
current SCL pulse. Remember that the master gener-
ates all SCL clock pulses including when it is reading
bits from the slave.
Acknowledgement (ACK and NACK): An acknowledge-
ment (ACK) or not acknowledge (NACK) is always the 9th
bit transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a write
operation) performs an ACK by transmitting a zero during
the 9th bit. A device performs a NACK by transmitting a
one during the 9th bit. Timing (Figure 2) for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgement that the device is properly receiving
data. A NACK is used to terminate a read sequence or as
an indication that the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave returns control of
SDA to the master.
Slave Address Byte: Each slave on the I²C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS4520’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure
1. Address pins connected to GND result in a ‘0’ in the
corresponding bit position in the slave address.
Conversely, address pins connected to V_CC result in a
‘1’ in the corresponding bit positions.
When the R/W bit is 0 (such as in A0h), the master is
indicating it will write data to the slave. If R/W = 1, (A1h
in this case), the master is indicating it will read from
the slave.
SDA
t_BUF
t_LOW
t_R
t_F
SCL
t_HD:STA
t_HIGH
STOP
START
NOTE: TIMING IS REFERENCED TO V_IL(MAX) AND V_IH(MIN)
t_HD:DAT
t_SU:DAT
t_HD:STA
t_SU:STA
REPEATED
START
Figure 2. I²C Timing Diagram
8 _____________________________________________________________________
t_SP
t_SU:STO