MAX1536 Datasheet, PDF (8/19 Pages) Maxim Integrated Products – 3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-Down Regulator with Dynamic Output Voltage Control

3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
Pin Description
PIN NAME
FUNCTION
1, 21,
24, 26
LX ^{Inductor Connection. Connection for the drains of the PMOS power switch and NMOS synchronous-rectifier}
switch. Connect all LX pins together.
2, 3,
19, 20
4
5
6
7
8, 25
IN Power Input. Power input for the internal PMOS switch. Connect all IN pins together.
SHDN
SKIP
FB
COMP
N.C.
Shutdown Control Input. Drive SHDN low to disable the reference, control circuitry, and internal MOSFETs.
Drive SHDN high or connect to V_CC for normal operation.
Pulse-Skipping Control Input. Connect SKIP to V_CC for low-noise, forced-PWM mode. Connect SKIP to AGND
for high-efficiency Idle Mode.
Feedback Input. The voltage at REFIN sets the feedback regulation voltage (V_FB = V_REFIN).
Integrator Compensation. Connect a 470pF capacitor from COMP to V_CC for integrator compensation.
See the Integrator Amplifier section.
No Connection. Not internally connected. Connecting pin 25 to LX eases PC board layout.
Off-Time Select Input. Sets the PMOS power switch off-time during constant off-time operation. Connect a
9
TOFF resistor from TOFF to AGND to adjust the PMOS switch off-time. See the Programming the No-Load Switching
Frequency and Off-Time section.
10
GATE
Buffered OD and OD Control Input. A logic low on GATE forces OD low and OD high impedance. A logic high
on GATE forces OD high impedance and OD low.
11
OD Open-Drain Output. A logic low on GATE forces OD high impedance. A logic high on GATE forces OD low.
12
OD ^{Inverted Open-Drain Output. A logic low on GATE forces OD low. A logic high on GATE forces OD high}
impedance.
13
REFIN External Reference Input. The voltage at REFIN sets the feedback regulation voltage (V_FB = V_REFIN).
14
REF
+2.0V Reference Voltage Output. Bypass REF to AGND with a minimum capacitance of 0.22µF. REF supplies
up to 50µA for external loads. The internal reference turns off in shutdown.
15 AGND Analog Ground. Connect backside pad to AGND.
16
V_CC
Analog Power Input. Power input to the internal analog circuitry. Bypass V_CC with a 10Ω and 2.2µF (min)
lowpass filter (Figure 1).
Fault-Blanking Control Input. FBLANK is a four-level logic input that enables or disables fault blanking, and sets
the minimum forced-PWM operation time (t_FBLANK). Enabling fault blanking forces PGOOD high for the selected
time period after a transition is detected on GATE. Additionally, the controller enters forced-PWM mode for the
duration of t_FBLANK anytime GATE changes states. Connect FBLANK to the following pins to select t_FBLANK and
17 FBLANK fault blanking:
V_CC = 150µs (typ), fault blanking enabled
Open = 100µs (typ), fault blanking enabled
REF = 50µs (typ), fault blanking enabled
AGND = 100µs (typ), fault blanking disabled
Open-Drain Power-Good Output. PGOOD is low during soft-start, in shutdown, and when the output voltage is
18
PGOOD
more than 10% (typ) above or below the normal regulation point. After the soft-start, PGOOD becomes high
impedance if the output is in regulation. PGOOD is blanked—forced into a high-impedance state—when
FBLANK is enabled and a transition is detected on GATE.
22, 23, _PGND Power Ground. Internally connected to the source of the internal NMOS synchronous-rectifier switch.
27, 28
Connect all PGND pins together.
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