MAX1536 Datasheet, PDF (3/19 Pages) Maxim Integrated Products – 3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-Down Regulator with Dynamic Output Voltage Control

3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V_IN = V_CC = V_SHDN = +3.3V, V_REFIN = +1.5V, SKIP = AGND, T_A = 0°C to +85°C, unless otherwise noted. Typical
values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Shutdown Supply Currents
I_CC + I_IN
I_IN
I_LX
SHDN = AGND; current into V_CC and IN;
LX = 0 or +3.3V
SHDN = AGND; current into IN; LX = 0
SHDN = AGND; current into LX; LX = +3.3V
0.2
20
µA
0.2
20
0.1
20
REFERENCE
REF Voltage
REF Load Regulation
REFIN Input Voltage Range
REFIN Input Bias Current
FAULT DETECTION
V_REF V_CC = V_IN = +3.0V to +5.5V
1.985 2.000 2.015
V
I_REF = -1µA to +50µA
10
mV
V_REFIN V_CC = V_IN = +3.0V to +5.5V, V_CC > V_REFIN + 1.35V
0.7
2.0
V
I_REFIN V_REFIN = 1.5V, V_FB = 1.01 × V_REFIN
-50
+50
nA
Thermal Shutdown
T_SHDN Rising, hysteresis = 15°C
165
°C
Undervoltage Lockout
Threshold
PGOOD Lower Trip Threshold
V_CC and V_IN rising, hysteresis 60mV typical
2.4
2.6
2.8
V_CC - V_REFIN, V_CC rising, hysteresis 60mV typical
0.9 1.35
V
V_CC - V_FB, V_CC rising, hysteresis 60mV typical
0.9 1.35
No load, falling edge, hysteresis = 1% (Note 4)
-12.5 -10 -8.0
%
PGOOD Upper Trip Threshold
No load, rising edge, hysteresis = 1% (Note 4)
+8.0 +10 +12.5 %
PGOOD Propagation Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
t_PGOOD
FB forced 2% beyond PGOOD trip threshold
I_SINK = 1mA
High-impedance state, forced to +5.5V
5
µs
0.1
V
1
µA
Fault Blanking Time
t_FBLANK
FBLANK = V_CC
FBLANK = open or AGND
FBLANK = REF
112 150 188
75
100 125
µs
37
50
63
INPUTS AND OUTPUTS
Logic Input Threshold
V _SHDN,
V _SKIP,
V_GATE
SHDN, SKIP, GATE, V_IN = V_CC = +3.3V,
rising edge, hysteresis = 100mV
SHDN, SKIP, GATE, V_IN = V_CC = +5.0V,
rising edge, hysteresis = 100mV
0.9
1.3
1.6
V
1.15 1.55 1.95
Logic Input Current
SHDN, SKIP, GATE
-0.5
+0.5 µA
FBLANK Logic Thresholds
V_FBLANK
FBLANK = V_CC
FBLANK = REF
FBLANK = open
V_CC - 0.2
1.8
0.8
2.2
V
1.2
FBLANK = AGND
0.2
FBLANK Input Current
OD On-Resistance
OD Leakage Current
OD On-Resistance
OD Leakage Current
I_FBLANK
R_OD
R _OD
FBLANK forced to AGND or V_CC
GATE = V_CC
GATE = AGND, V_OD = +5.5V
GATE = AGND
GATE = V_CC, V_OD = +5.5V
-5
+5
µA
10
25
Ω
-50
+50
nA
10
25
Ω
-50
+50
nA
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