MAX1536 Datasheet, PDF (16/19 Pages) Maxim Integrated Products – 3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-Down Regulator with Dynamic Output Voltage Control

3.6A, 1.4MHz, Low-Voltage, Internal-Switch Step-
Down Regulator with Dynamic Output Voltage Control
Applications Information
Multioutput Voltage Settings
The MAX1536 is optimized to work in applications that
require two dynamic output voltages; however, discrete
logic or a DAC connected to REFIN allows three or
more dynamic output voltages.
Figure 6 shows an application circuit providing four
voltage levels using discrete logic. Switching resistors
in and out of the resistor network changes the voltage
at REFIN. An edge-detection circuit is added to trigger
a 1µs pulse on GATE to start the fault-blanking and
forced-PWM operation. GATE requires a minimum
pulse width of 500ns. The edge-detection circuit is not
required if the MAX1536 is always in PWM mode (SKIP
= V_CC) and fault blanking is not necessary.
Active Bus Termination
Active bus termination power supplies generate a volt-
age rail that tracks a set reference. Active bus termina-
tion power supplies are unique because they source
and sink current. DDR memory architecture requires
active bus termination. In DDR memory architecture,
the termination voltage is set at exactly half the memory
supply voltage. Configure the MAX1536 to generate the
termination voltage using a resistor-divider at REFIN.
Force the MAX1536 to operate in PWM mode (SKIP =
V_CC) to source and sink current. Figure 7 shows the
MAX1536 configured as a DDR termination regulator.
Connect GATE and FBLANK to AGND when unused.
Circuit Layout and Grounding
Good layout is necessary to achieve the intended out-
put power level, high efficiency, and low noise. Good
layout includes the use of a ground plane, careful com-
ponent placement, and correct routing of traces using
appropriate trace widths. Refer to the MAX1536 EV Kit
for layout reference.
V_DDQ
1000pF
1000pF
V_CC
SKIP
IN
10kΩ
MAX1536 _FB
REFIN
L
LX
10kΩ
AGND
PGND
V_IN
C_IN
V_TT
=
VDDQ
2
C_OUT
GATE
FBLANK
OD
OD
V_DDQ = DDR MEMORY SUPPLY VOLTAGE
V_TT = TERMINATION SUPPLY VOLTAGE
Figure 7. Active Bus Termination
R4
REF
R1
B
R3
REFIN
A
C1
R2
MAX1536
AGND
1.5kΩ
OD
OD
1000pF
GATE
1.5kΩ
1000pF
V_OUT
50mV/div
V_LX
0
5V/div
0
I_LX
2A/div
10μs/div
V_IN = 3.3V, V_OUT = 1.25V, I_OUT = -1A TO +1A TO -1A
Figure 6. Multioutput Voltage Settings
Figure 8. Source/Sink Waveforms
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