Z86L88 Datasheet, PDF (72/80 Pages) Zilog, Inc. – INFRARED REMOTE CONTROLLERS

Z86L88
Low-Voltage IR Microcontroller
65
Table 24. SMR2(F)0Dh: Stop-Mode Recovery Register 2
Field
Bit Position
Value Description
Reserved
7-------
0
Reserved (Must be 0)
Recovery Level
-6------
W
0*
Low
1
High
Reserved
--5-----
0
Reserved (Must be 0)
Source
---432--
W
000* A. POR Only
001
B. NAND of P23–P20
010
C. NAND or P27–P20
011
D. NOR of P33–P31
100
E. NAND of P33–P31
101
F. NOR of P33–P31, P00, P07
110
G. NAND of P33–P31, P00, P07
111
H. NAND of P33–P31, P22–P20
Reserved
------10
00
Reserved (Must be 0)
Notes:
*Indicates the value upon Power-On Reset
Port pins configured as outputs are ignored as a SMR recovery source.
Watch-Dog Timer Mode Register (WDTMR)
The WDT is a retriggerable, one-shot timer that resets the Z8 if it reaches its ter-
minal count. The WDT must initially be enabled by executing the WDT instruction
and refreshed on subsequent executions of the WDT instruction. The WDT circuit
is driven by an on-board RC oscillator or external oscillator from the XTAL1 pin.
The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is selected with bit 4 of the WDT register. Bits 0 and 1 con-
trol a tap circuit that determines the minimum time-out period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 50). This register is accessible only
during the first 61 processor cycles (122 XTAL clocks) from the execution of the
first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode Recov-
ery (Figure 50). After this point, the register cannot be modified by any means,
intentional or otherwise. The WDTMR cannot be read. The register is located in
Bank F of the Expanded Register Group at address location 0FH. The WDTMR is
organized as shown in Figure 50.
19-4614; Rev 0; 4/09