MAX1332 Datasheet, PDF (7/25 Pages) Maxim Integrated Products – 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs

3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
TIMING CHARACTERISTICS (MAX1333) (Figure 4)
(AV_DD = +2.7V to +3.6V, DV_DD = +2.7V to AV_DD, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SCLK Clock Period
SCLK Pulse Width
CNVST Rise to DOUT Disable
CNVST Fall to DOUT Enable
CHSEL to CNVST Fall Setup
BIP/UNI to CNVST Fall Setup
CNVST Fall to CHSEL Hold
SCLK Fall to BIP/UNI Hold
DOUT Remains Valid After SCLK
SCLK Rise to DOUT Transition
CNVST to SCLK Rise
SCLK Rise to CNVST
CNVST Pulse Width
Minimum Recovery Time (Full
Power-Down)
SYMBOL
t_CP
t_CPW
t_CRDD
t_CFDE
t_CHCF
t_BUCF
t_CFCH
t_CFBU
t_DHOLD
t_DOT
t_SETUP
t_HOLD
t_CSW
CONDITIONS
C_LOAD = 0pF (Note 4)
C_LOAD = 30pF
t_FPD From CNVST fall or SHDN rise
MIN TYP MAX UNITS
31.2
ns
10
ns
15
ns
15
ns
50
ns
50
ns
0
ns
0
ns
1
2
ns
6
ns
6
ns
0
ns
6
ns
4
µs
Minimum Recovery Time (Partial
Power-Down)
t_PPD From CNVST fall
500
ns
Note 3: Tested with AV_DD = DV_DD = +2.7V.
Note 4: Guaranteed by design, not production tested.
DOUT
6kΩ
30pF
DGND
a) HIGH IMPEDANCE TO V_OH, V_OL TO V_OH,
AND V_OH TO HIGH IMPEDANCE
Figure 1. Load Circuits for Enable/Disable Times
DV_DD
6kΩ
DOUT
30pF
DGND
b) HIGH IMPEDANCE TO V_OL, V_OH TO V_OL,
AND V_OL TO HIGH IMPEDANCE
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