MAX1332 Datasheet, PDF (16/25 Pages) Maxim Integrated Products – 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs

3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
SCLK
DOUT
1
13
16
1
0
0
0 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
0
0
Figure 6. Continuous Conversion with Burst or Continuous Clock
CNVST
SCLK
DOUT
ONE 8-BIT TRANSFER
CONVST MUST GO HIGH AFTER 4TH BUT BEFORE 13TH SCLK RISING EDGE
1ST SCLK RISING EDGE
0
0
0 D11 D10 D9 D8 D7
DOUT GOES HIGH IMPEDANCE ONCE CONVST GOES HIGH
MODE
NORMAL
PPD
Figure 7. SPI Interface—Partial Power-Down
rising SCLK edges are needed to clock out the three
leading zeros, 12 data bits, and a trailing zero. For con-
tinuous operation, pull CNVST high between the 14th
and the 15th rising edges of SCLK. The highest
throughput is achieved when performing continuous
conversions. If CNVST is low during the rising edge of
the 16th SCLK, the DOUT line goes to a high-imped-
ance state on either CNVST’s rising edge or the next
SCLK’s rising edge, enabling the serial interface to be
shared by multiple devices. Figure 6 illustrates a con-
version using a typical serial interface.
Partial Power-Down (PPD) and Full Power-
Down (FPD) Mode
Power consumption is reduced significantly by placing
the MAX1332/MAX1333 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast
wake-up time applications. Once CNVST is transitioned
from high to low, pull CNVST high any time after the 4th
rising edge of the SCLK but before the 13th rising edge
of the SCLK to enter partial power-down mode (see
Figure 7). Drive CNVST low and then drive high before
the 4th SCLK to remain in partial power-down mode. This
reduces the supply current to 3.3mA. Drive CNVST low
and allow at least 13 SCLK cycles to elapse before dri-
ving CNVST high to exit partial power-down mode.
Full power-down mode reduces the supply current to
0.2µA and is ideal for infrequent data sampling. To
enter full power-down mode, the MAX1332/MAX1333
must first be in partial power-down mode. While in par-
tial power-down mode, repeat the sequence used to
enter partial power-down mode to enter full power-
down mode (see Figure 8). Drive CNVST low and allow
at least 13 SCLK cycles to elapse before driving
CNVST high to exit full power-down mode.
Maintain a logic low or a logic high on SCLK and all
digital inputs at DV_DD or DGND while in either partial
power-down or full power-down mode to minimize
power consumption.
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