MAX1332 Datasheet, PDF (15/25 Pages) Maxim Integrated Products – 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs

3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
CNVST
t_SETUP
SCLK
t_CP
DOUT
t_CFDE
Figure 4. Detailed Serial-Interface Timing
t_DOT
t_DHOLD
t_HOLD
t_CSW
t_CRDD
CNVST
SCLK
t_CONV
t_SETUP
POWER- MODE SELECTION WINDOW
t_ACQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
DOUT ^HIGH-Z
ANALOG
INPUT TRACK
AND HOLD STATE
00
Figure 5. Interface Timing Sequence
CONTINUOUS-CONVERSION
SELECTION WINDOW
0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0
HOLD
TRACK
modes, the input common-mode voltage can vary as
long as the voltage at any single analog input (V_{AIN_P},
V_{AIN_N}) remains within 50mV of the analog power sup-
ply rails (AV_DD, AGND).
As shown in Figure 3, internal protection diodes confine
the analog input voltage within the region of the analog
power-supply rails (AV_DD, AGND) and allow the analog
input voltage to swing from AGND - 0.3V to AV_DD + 0.3V
without damage. Input voltages beyond AGND - 0.3V
and AV_DD + 0.3V forward bias the internal protection
diodes. In this situation, limit the forward diode current to
50mA to avoid damaging the MAX1332/MAX1333.
Serial Digital Interface
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CNVST and SCLK digital inputs. CNVST
controls the state of the T/H as well as when a conver-
sion is initiated. CNVST also controls the power-down
mode of the device (see the Partial Power-Down (PPD)
and Full Power-Down (FPD) Mode section). SCLK
clocks data out of the serial interface and sets the con-
version speed. Figures 4 and 5 show timing diagrams
that outline the serial-interface operation.
Starting a Conversion
On power-up, the MAX1332/MAX1333 enter full power-
down mode. The first rising edge of CNVST exits the full
power-down mode and the MAX1332/MAX1333 begin
acquiring the analog input. A CNVST falling edge initi-
ates a conversion sequence. The T/H stage holds the
input voltage; DOUT changes from high impedance to
logic low; and the ADC begins to convert at the first
SCLK rising edge. SCLK is used to drive the conver-
sion process, and it shifts data out of DOUT. SCLK
begins shifting out the data after the 4th rising edge of
SCLK. DOUT transitions t_DOT after each SCLK’s rising
edge and remains valid for t_DHOLD after the next rising
edge. The 4th rising clock edge produces the MSB of
the conversion result at DOUT, and the MSB remains
valid t_DHOLD after the 5th rising edge of SCLK. Sixteen
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