MAX1332 Datasheet, PDF (4/25 Pages) Maxim Integrated Products – 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs

3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (MAX1332) (continued)
(AV_DD = +4.75V to +5.25V, DV_DD = +2.7V to +3.6V, f_SCLK = 48MHz, V_REF = 4.096V, T_A = T_MIN to T_MAX, unless otherwise noted.
Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Average current (f_SAMPLE = 3MHz, f_SCLK =
48MHz, zero-scale input)
4.5
7
mA
Digital Supply Current
Power-Supply Rejection
I_DVDD
PSR
Power-down (f_SCLK = 48MHz), CNVST =
DV_DD
Static; all digital inputs are connected to
DV_DD or DGND
AV_DD = 4.75V to 5.25V, full-scale input
15
30
µA
0.2
2
±2
mV
TIMING CHARACTERISTICS (MAX1332) (Figure 4)
(AV_DD = +4.75V to +5.25V, DV_DD = +2.7V to +3.6V, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SCLK Clock Period
SCLK Pulse Width
CNVST Rise to DOUT Disable
CNVST Fall to DOUT Enable
CHSEL to CNVST Fall Setup
BIP/UNI to CNVST Fall Setup
CNVST Fall to CHSEL Hold
SCLK Fall to BIP/UNI Hold
DOUT Remains Valid After SCLK
SCLK Rise to DOUT Transition
CNVST to SCLK Rise
SCLK Rise to CNVST
CNVST Pulse Width
Minimum Recovery Time (Full
Power-Down)
SYMBOL
t_CP
t_SPW
t_CRDD
t_CFDE
t_CHCF
t_BUCF
t_CFCH
t_CFBU
t_DHOLD
t_DOT
t_SETUP
t_HOLD
t_CSW
CONDITIONS
C_LOAD = 0pF (Note 2)
C_LOAD = 30pF
t_FPD From CNVST fall or SHDN rise
MIN TYP MAX UNITS
20.8
ns
6
ns
15
ns
15
ns
40
ns
40
ns
0
ns
0
ns
1
2
ns
6
ns
6
ns
0
ns
6
ns
4
µs
Minimum Recovery Time (Partial
Power-Down)
t_PPD From CNVST fall
500
ns
Note 1: Tested with AV_DD = 4.75V and DV_DD = +2.7V.
Note 2: Guaranteed by design, not production tested.
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