MAX1204 Datasheet, PDF (7/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
__________________________________________Typical Operating Characteristics
(V_DD = 5V ±5%; VL = 2.7V to 3.6V; f_SCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
4.7µF capacitor at REF; T_A = +25°C; unless otherwise noted.)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.0
1.8
SUPPLY CURRENT
vs. TEMPERATURE
2.0
1.8
SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
6
REFADJ = GND
5
4
1.6
1.6
3
1.4
1.4
2
1.2
1.2
1
1.0
4.5 4.7 4.9 5.1 5.3 5.5
SUPPLY VOLTAGE (V)
1.0
-60 -20 20
60 100 140
TEMPERATURE (°C)
0
-60 -20
20
60 100 140
TEMPERATURE (°C)
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
9
V_SS
Negative Supply Voltage. Tie V_SS to -5V ±5% or GND.
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1204 down to 10µA (max) supply
10
SHDN
current; otherwise, the MAX1204 is fully operational. Pulling SHDN to V_DD puts the reference-buffer
amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in
external compensation mode.
Reference Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
11
REF
provides a 4.096V nominal output, externally adjustable at REFADJ. In external reference mode,
disable the internal buffer by pulling REFADJ to V_DD.
12
REFADJ
Input to the Reference-Buffer Amplifier. Tie REFADJ to V_DD to disable the reference-buffer amplifier.
13
GND
Ground; IN- Input for Single-Ended Conversions
14
VL
Supply Voltage for Digital Output Pins. Voltage applied to VL determines the positive output swing of
the Digital Outputs (DOUT, SSTRB).
15
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX1204 begins the analog-
16
SSTRB
to-digital conversion and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
CS
Active-Low Chip Select. Data is not clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
19
SCLK
Serial-Clock Input. SCLK clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed. (Duty cycle must be 40% to 60% in external clock mode.)
20
V_DD
Positive Supply Voltage, +5V ±5%
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