MAX1204 Datasheet, PDF (14/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
CS
SCLK
1 2 345678
9 10 11 12
DIN
SSTRB
DOUT
ADC STATE
SEL2 SEL1 SEL0
UNI/
DIP
SGL/
DIF
PD1
PD0
START
t_CONV
ACQUISITION _CONVERSION
IDLE
1.5µs
(SCLK = 2MHz)
10µs MAX
B9
MSB
B8
B7
Figure 9. Internal Clock Mode Timing
18 19 20 21 22 23 24
B0
LSB
S1
FILLED WITH
S0 _ZEROS
IDLE
CS • • •
SSTRB • • •
SCLK • • •
t_CONV
t_CSH
t_SSTRB
t_CSS
t_SCK
PD0 CLOCK IN
Figure 10. Internal Clock Mode SSTRB Detailed Timing
NOTE: KEEP SCLK LOW DURING CONVERSION FOR BEST NOISE PERFORMANCE.
Data Framing
CS’s falling edge does not start a conversion on the
MAX1204. The first logic high clocked into DIN is inter-
preted as a start bit and defines the first bit of the control
byte. A conversion starts on SCLK’s falling edge after the
eighth bit of the control byte (the PD0 bit) is clocked into
DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any-
time the converter is idle; (e.g., after V_DD is applied).
or
The first high bit clocked into DIN after bit 3 (B3) of a
conversion in progress appears at DOUT.
If a falling edge on CS forces a start bit before B3
becomes available, the current conversion is termi-
nated and a new one started. Thus, the fastest the
MAX1204 can run is 15 clocks/conversion. Figure 11a
shows the serial-interface timing necessary to perform
a conversion every 15 SCLK cycles in external clock
mode. If CS is low and SCLK is continuous, guarantee
a start bit by first clocking in 16 zeros.
Most microcontrollers (µCs) require that conversions
occur in multiples of eight SCLK clocks; 16 clocks per
conversion is typically the fastest that a µC can drive
the MAX1204. Figure 11b shows the serial-interface
timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
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