MAX1204 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
Table 1a. Unipolar Full Scale
and Zero Scale
REFERENCE
Internal
External
at REFADJ
at REF
ZERO
SCALE
0V
0V
0V
FULL SCALE
+4.096V
V_REFADJ x 1.68
V_REF
Input Bandwidth
The ADC’s input tracking circuitry has a 4.5MHz
small-signal bandwidth. Therefore, it is possible to digi-
tize high-speed transient events and measure periodic
signals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Range and Input Protection
Internal protection diodes, which clamp the analog
inputs to V_DD and V_SS, allow the analog input pins to
swing from (V_SS - 0.3V) to (V_DD + 0.3V) without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed V_DD by more than 50mV, or
be lower than V_SS by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off-channels over 2mA, as excessive current
degrades on-channel conversion accuracy.
The full-scale input voltage depends on the voltage at
REF (Tables 1a and 1b).
Quick Look
Use the circuit of Figure 5 to quickly evaluate the
MAX1204’s analog performance. The MAX1204 requires
that a control byte be written to DIN before each conver-
sion. Tying DIN to +3V feeds in control byte $FF hex,
Table 1b. Bipolar Full Scale, Zero Scale,
and Negative Full Scale
REFERENCE
Internal
External
at
REFADJ
at REF
NEGATIVE
FULL SCALE
ZERO
SCALE
FULL SCALE
-4.096V/2
0V +4.096V / 2
-1/2 V_REFADJ x
1.68
0V
+1/2 V_REFADJ
x 1.68
-1/2 V_REF
0V
+1/2 V_REF
which triggers single-ended unipolar conversions on
CH7 in external clock mode without powering down
between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the conversion result shifts out
of DOUT. Varying the analog input to CH7 alters the
sequence of bits from DOUT. A total of 15 clock cycles
per conversion is required. All SSTRB and DOUT output
transitions occur on SCLK’s falling edge.
How to Start a Conversion
Clocking a control byte into DIN starts conversion on
the MAX1204. With CS low, each rising edge on SCLK
clocks a bit from DIN into the MAX1204’s internal shift
register. After CS falls, the first logic “1” bit defines the
control byte’s MSB. Until this first “start” bit arrives, any
number of logic “0” bits can be clocked into DIN with
no effect. Table 2 shows the control-byte format.
The MAX1204 is fully compatible with Microwire and SPI
devices. For SPI, select the correct clock polarity and
sampling edge in the SPI control registers: set CPOL =
0 and CPHA = 0. Microwire and SPI both transmit a byte
and receive a byte at the same time. Using the Typical
Operating Circuit, the simplest software interface
requires only three 8-bit transfers to perform a con-
version (one 8-bit transfer to configure the ADC, and two
more 8-bit transfers to clock out the conversion result).
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