MAX1204 Datasheet, PDF (6/24 Pages) Maxim Integrated Products – 5v, 8-cHANNEL, sERIAL, 10-bIT adc WITH 3v dIGITAL iNTERFACE

5V, 8-Channel, Serial, 10-Bit ADC
with 3V Digital Interface
TIMING CHARACTERISTICS
(V_DD = +5V ±5%, VL = 2.7V to 3.6V, V_SS = 0V or -5V ±5%, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Acquisition Time
t_ACQ
1.5
DIN to SCLK Setup
t_DS
100
DIN to SCLK Hold
t_DH
SCLK Fall to Output Data Valid
t_DO
C_LOAD = 100pF
20
CS Fall to Output Enable
t_DV
C_LOAD = 100pF
CS Rise to Output Disable
t_TR
C_LOAD = 100pF
CS to SCLK Rise Setup
t_CSS
100
CS to SCLK Rise Hold
t_CSH
0
SCLK Pulse Width High
t_CH
200
SCLK Pulse Width Low
t_CL
200
SCLK Fall to SSTRB
t_SSTRB C_LOAD = 100pF
CS Fall to SSTRB Output Enable
(Note 6)
t_SDV External clock mode only, C_LOAD = 100pF
CS Rise to SSTRB Output
Disable (Note 6)
t_STR External clock mode only, C_LOAD = 100pF
SSTRB Rise to SCLK Rise
(Note 6)
t_SCK Internal clock mode only
0
MAX
0
240
240
240
240
UNITS
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
240
ns
240
ns
ns
Note 1: Tested at V_DD = 5.0V; V_SS = 0V; unipolar input mode.
Note 2: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is
calibrated.
Note 3: Internal reference, offset nulled.
Note 4: On-channel grounded; sine-wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for analog inputs is from V_SS to V_DD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: Shutdown supply current is measured with VL at 3.3V, and with all digital inputs tied to either VL or GND (Figure 12c);
REFADJ = GND.
Note 10: Logic supply current is measured with the digital outputs (DOUT and SSTRB) disabled (CS high). When the outputs are
active (CS low), the logic supply current depends on f_SCLK, and on the static and capacitive load at DOUT and SSTRB.
Note 11: Measured at V_SUPPLY +5% and V_SUPPLY -5% only.
Note 12: Measured at VL = 2.7V and VL = 3.6V.
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