DS8313 Datasheet, PDF (7/18 Pages) Maxim Integrated Products – Smart Card Interface

Smart Card Interface
Pin Description
PIN
1, 2
3
4
5, 7, 8, 9,
12, 13, 27,
28
6, 18
10
11
14
15
16
17
19
20
21
22
23
24, 25
26
NAME
CLKDIV1,
CLKDIV2
5V/3V
1_8V
FUNCTION
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high
selects 5V operation; logic-low selects 3V operation. The 1_8V pin overrides the setting on this pin if
active. See Table 3 for a complete description of choosing card voltages.
1.8V Operation Selection. Active-high selection for 1.8V smart card communication. An active-high
signal on this pin overrides any setting on the 5V/3V pin.
N.C.
No Connection/Don’t Care. These pins are not bonded out.
V_DDA
(N.C.)
PRES
I/O
CGND
CLK
RST
V_CC
CMDVCC
RSTIN
V_DD
GND
OFF
XTAL1,
XTAL2
I/OIN
Analog (Smart Card) Supply. Connect to 5V power supply. Pin 18 is N.C. for the DS8314.
Card Presence Indicator. Active-high card presence input from the DS8313 to the microcontroller.
When the presence indicator becomes active, a debounce timeout begins. After 8ms (typ), the OFF
signal becomes active. A trim optim defines whether or not the part provides active-low presence
detection.
Smart Card Data-Line Output. Card data communication line, contact C7.
Smart Card Ground
Smart Card Clock. Card clock, contact C3.
Smart Card Reset. Card reset output from contact C2.
Smart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m
).
Activation Sequence Initiate. Active-low input from host.
Card Reset Input. Reset input from the host.
Supply Voltage
Digital Ground
Status Output. Active-low interrupt output to the host. Includes a 24k
integrated pullup resistor to
V_DD.
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on
XTAL1.
I/O Input. Host-to-interface chip data I/O line.
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