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| DS5003 Datasheet, PDF (7/24 Pages) Maxim Integrated Products – Secure Microprocessor Chip | |||
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Secure Microprocessor Chip
AC CHARACTERISTICSâPROG
(VCC = 5V ±10%, TA = 0°C to +70°C.)
PARAMETER
PROG Low to Active
PROG High to Inactive
SYMBOL
MIN
tPRA
48
tPRI
48
MAX
UNITS
Clocks
Clocks
Note 1: All voltages are referenced to ground.
Note 2: Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10ns, VIL = 0.5V;
XTAL2 disconnected; RST = Port 0 = VCC, MSEL = VSS.
Note 3: Idle mode, IIDLE, is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10ns, VIL = 0.5V; XTAL2
disconnected; Port 0 = VCC, RST = MSEL = VSS.
Note 4: Stop mode, ISTOP, is measured with all output pins disconnected; Port 0 = VCC; XTAL2 not connected; RST = MSEL =
XTAL1 = VSS.
Note 5: Pin capacitance is measured with a test frequency: 1MHz, TA = +25°C. This specification is characterized but not produc-
tion tested.
Note 6: VCCO2 is measured with VCC < VLI and a maximum load of 10µA on VCCO.
Note 7: ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation.
Note 8:
Note 9:
ILI is the current drawn from the VLI input when VCC = 0V and VCCO is disconnected. Battery-backed mode is 2.5V ⤠VBAT
⤠4.0; VCC ⤠VBAT; VSDI should be ⤠VILS for IBAT max.
PF pin operation is specified with VBAT ⥠3.0V.
Note 10: VIHS minimum is 2.0V or VCCO, whichever is lower.
Note 11: SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitcher, but SDI is
not guaranteed unless it is longer than tSPA.
Note 12: Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is
first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the
crystal vendor for a worst-case specification on this time.
ALE
RD
PORT 0
PORT 2
tALPW
tRDHALH
tALLRDL
tALLVD
tRDPW
tAVALL
tAVAAV
A7âA0
(Rn OR DPL)
tRDLDV
tRDLAZ
tRDHDV
DATA IN
tRDHDZ
tAVRDL
tAVDV
P2.7âP2.0 OR A15âA8 FROM DPH
A7âA0
(PCL)
INSTR
IN
A15âA8 FROM PCH
Figure 1. Expanded Data Memory Read Cycle
_______________________________________________________________________________________ 7
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