MAX1358B Datasheet, PDF (66/71 Pages) Maxim Integrated Products – 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
For self-calibration, the offset value is the RAW result
when the inputs are shorted internally and the gain value
is 1/(RAW - OFFSET) with the reference connected to the
input. This is done automatically when these modes are
selected. The self-offset and gain calibration corrects for
errors internal to the ADC and the results are stored and
used automatically in the OFFSET CAL and GAIN CAL
registers. For best results, use the ADC in the same con-
figuration as the calibration. This pertains to conversion
rate only because the PGA gain and unipolar/bipolar
modes are performed digitally.
For system calibration, the offset and gain values cor-
rect for errors in the whole signal path including the
internal ADC and any external circuits in the signal
path. For the system calibration, a user-provided zero-
input condition is required for the offset calibration and
a user-provided full-scale input is required for the gain
calibration. These values are automatically written to
the OFFSET CAL and GAIN CAL registers. The order of
the calibrations should be offset followed by gain.
The offset correction value is in two’s complement. The
default value is 000000h, 00...00b, or 0 decimal.
The gain correction value is an unsigned binary number
with 23 bits to the right of the decimal point. The largest
number is therefore 1.1111...1b = 2 - 2^-23 and the small-
est is 0.000...0b = 0, although it does not make sense to
use a number smaller than 0.1000...0b = 0.5. The default
value is 800000h, 1.000...0b or 1 decimal.
Changing the offset or gain calibration values does not
affect the value in the DATA register until a new conver-
sion has completed. This applies to all the mode bits
for PGA gain, unipolar/bipolar, etc.
Grounding and Layout
For best performance, use a PCB with separate analog
and digital ground planes.
Design the PCB so that the analog and digital sections
are separated and confined to different areas of the
board. Join the digital and analog ground planes at one
point. If the DAS is the only device requiring an AGND-to-
DGND connection, connect planes to the AGND pin of the
DAS. In systems where multiple devices require AGND-to-
DGND connections, the connection should still be made
at only one point. Make the star ground as close as possi-
ble to the MAX1358B.
Avoid running digital lines under the device because
these may couple noise onto the device. Run the ana-
log ground plane under the MAX1358B to minimize
coupling of digital noise. Make the power-supply lines
to the MAX1358B as wide as possible to provide low-
impedance paths and reduce the effects of glitches on
the power-supply line.
Shield fast-switching signals such as clocks with digital
ground to avoid radiating noise to other sections of the
board. Avoid running clock signals near the analog
inputs. Avoid crossover of digital and analog signals.
Good decoupling is important when using high-resolu-
tion ADCs. Decouple all analog supplies with 10µF
capacitors in parallel with 0.1µF HF ceramic capacitors
to AGND. Place these components as close to the
device as possible to achieve the best decoupling.
Crystal Layout
Follow basic layout guidelines when placing a crystal
on a PCB with a DAS to avoid coupled noise:
1) Place the crystal as close as possible to 32KIN and
32KOUT. Keeping the trace lengths between the
crystal and inputs as short as possible reduces the
probability of noise coupling by reducing the length
of the “antennae”. Keep the 32KIN and 32KOUT
lines close to each other to minimize the loop area
of the clock lines. Keeping the trace lengths short
also decreases the amount of stray capacitance.
2) Keep the crystal solder pads and trace width to
32KIN and 32KOUT as small as possible. The larg-
er these bond pads and traces are, the more likely
it is that noise will couple from adjacent signals.
3) Place a guard ring (connect to ground) around the
crystal to isolate the crystal from noise coupled
from adjacent signals.
4) Ensure that no signals on other PCB layers run
directly below the crystal or below the traces to
32KIN and 32KOUT. The more the crystal is isolat-
ed from other signals on the board, the less likely it
is that noise will be coupled into the crystal.
Maintain a minimum distance of 5mm between any
digital signal and any trace connected to 32KIN or
32KOUT.
5) Place a local ground plane on the PCB layer imme-
diately below the crystal guard ring. This helps to
isolate the crystal from noise coupling from signals
on other PCB layers.
Note: The ground plane must be in the vicinity of the
crystal only and not on the entire board.
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