MAX1358B Datasheet, PDF (28/71 Pages) Maxim Integrated Products – 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Digital Filtering
The MAX1358B contains an on-chip digital lowpass fil-
ter that processes the data stream from the modulator
using a sinc⁴ (sinx/x)⁴ response. The sinc⁴ filter has a
settling time of four output data periods (4 x 200ms).
The MAX1358B has 25% overrange capability built into
the modulator and digital filter:
H(f)
=
⎡
⎢
⎢¹
⎢
⎢
N
⎣⎢
⎛
SIN_⎝⎜Nπ
f
f_m
⎞
⎠⎟
⎛
SIN_⎝⎜
π
f
f_m
⎞
⎠⎟
⎤⁴
⎥
⎥
⎥
⎥
⎦⎥
Figure 4 shows the filter frequency response. The sinc⁴
characteristic -3dB cutoff frequency is 0.228 times the
first notch frequency.
The output data rate for the digital filter corresponds
with the positioning of the first notch of the filter’s fre-
quency response. The notches of the sinc⁴ filter are
repeated at multiples of the first notch frequency. The
sinc⁴ filter provides an attenuation of better than 100dB
at these notches. For example, 50Hz is equal to five
times the first notch frequency and 60Hz is equal to six
times the first notch frequency.
0
-40
-80
-120
-160
-200
0
20 40 60 80 100 120
FREQUENCY (Hz)
Figure 4. Filter Frequency Response
Force-Sense DAC
The MAX1358B incorporates two 10-bit force-sensing
DACs. The DACs’ reference voltage sets the full-scale
range. Program the DACA_OP register using the serial
interface to set the output voltages of the DAC at OUTA.
Connecting resistors in a voltage-divider configuration
between OUTA, FBA, and GND sets a different closed-
loop gain for the output amplifier (see the Applications
Information section).
The DAC output amplifier typically settles to ±0.5 LSB
from a full-scale transition within 65µs (unity gain and
loaded with 10kΩ in parallel with 200pF). Loads of less
than 1kΩ could degrade performance. See the Typical
Operating Characteristics for the source-and-sink
capability of the DAC output.
The MAX1358B features a software-programmable
shutdown mode for the DAC. Power down DACA or
DACB independently or simultaneously by clearing the
DAE and DBE bits (see the DACA_OP Register and
DACB_OP Register sections). DAC output OUTA and
OUTB go high impedance when powered down. The
DACs are normally powered down at power-on reset.
Charge Pump
The charge pump provides > 3V at CPOUT with a maxi-
mum 10mA load. Enable the charge pump through the
PS_VMONS register. The charge pump is powered
from DV_DD. See Figures 5 and 6 for block diagrams of
the charge pump and linear regulator. The charge
pump is disabled at power-on reset.
An internal clock drives the charge-pump clock and
ADC clock. The charge pump delivers a maximum
10mA of current to external devices. The droop and the
ripple depend on the clock frequency (f_CLK =
32.768kHz/2), switch resistances (R_SWITCH = 5Ω), and
the external capacitors (10µF) along with their respec-
tive ESRs, as shown below.
V_DROOP = I_OUTR_OUT
R_OUT
=
1
f_CLKC_F
+
2R_SWITCH +
4ESR_CF
+ ESR_CCPOUT
V_RIPPLE
=
I_OUT
f_CLKC_CPOUT
+ 2I_OUTESR_CCPOUT
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