MAX1358B Datasheet, PDF (53/71 Pages) Maxim Integrated Products – 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
Table 16. UPIO Mode Configuration
UP4MD<3:0>,
UP3MD<3:0>,
UP2MD<3:0>, UP1MD<3:0>
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
MODE
GPI
GPO
SWA or SWA
SWB or SWB
SPDT1 or SPDT1
SPDT2 or SPDT2
DESCRIPTION
General-purpose digital input. Active edges detected by UPR_ or UPF_
status register bits. ALH_ has no effect with this setting.
General-purpose digital output. Logic level set by LL_ bit. ALH_ has no
effect with this setting.
Digital input. DAC A buffer switch control. See the SWA bit description in
the SW_CTRL Register section.
Digital input. DAC B buffer switch control. See the SWB bit description in
the SW_CTRL Register section.
Digital input. SPDT1 switch control. See the SPDT1<1:0> bit description in the
SW_CTRL Register section.
Digital input. SPDT2 switch control. See the SPDT2<1:0> bit description in the
SW_CTRL Register section.
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
SLEEP or SLEEP
WU or WU
Sleep-mode digital input. Overrides power-control register and puts the
part into sleep mode when asserted. The clock buffers must be powered
down separately. When deasserted, power mode is determined by the
SHDN bit.
Wake-up digital input. Asserted edge clears SHDN bit.
Reserved
Reserved. Do not use these settings.
PWM or PWM
PWM digital output. Signal defined by the PWM_CTRL register. PWM on
(or high or “1”); assertion level defined by the ALH_ bit. When PWM is
disabled (PWME = 0), the UPIO pin idles high (DV_DD or CPOUT) if
ALH = 1, and low (DGND) if ALH = 0.
1
1
0
0
SHDN or SHDN
Power-supply shutdown digital output. Equivalent to SHDN bit. Power-on
default of GPI with pullup ensures initial power-supply turn-on when UPIO
is connected to a power supply with a SHDN input.
1
1
0
1
AL_DAY or AL_DAY ^{RTC alarm digital output. Asserts for time-of-day alarm events; equivalent}
to ALD in STATUS register.
1
1
1
0
Reserved
Reserved. Do not use these settings.
1
1
1
1
DRDY or DRDY
ADC data-ready digital output. Asserts when analog-to-digital conversion
or calibration completes. Not masked by MADD bit.
Note: When multiple UPIO inputs are configured for the same input function, the inputs are ORed together.
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