MAX1358B Datasheet, PDF (54/71 Pages) Maxim Integrated Products – 16-Bit, Data-Acquisition System with ADC, DACs, UPIOs, RTC, Voltage Monitors, and Temp Sensor

16-Bit, Data-Acquisition System with ADC, DACs,
UPIOs, RTC, Voltage Monitors, and Temp Sensor
UPIO_SPI Register (Power-On State: 0000 XXXX)
MSB
UP4S
UP3S
UP2S
UP1S
The UPIO_SPI pass-through control register bits map
the serial interface signals to the UPIO pins, allowing
the DAS to drive other devices at CPOUT or DV_DD volt-
age levels, depending on the SV_ bit setting found in
the UPIO_CTRL register. Individual bits are provided to
set only the desired UPIO inputs to the SPI pass-
through mode. This mode becomes active when CS is
driven high to complete the write to this register, and
remains active as long as CS stays high (i.e., multiple
pass-through writes are possible). The SPI pass-
through mode is deactivated immediately when CS is
pulled low for the next DAS write.
The UPIO_ state (both before and after the SPI pass-
through mode) is set by the UP_MD<3:0> and LL_ bits.
When a UPIO is configured for SPI pass-through mode
and the CS is high, UPR_, UPF_, and LL_ continue to
detect UPIO_ edges, which can still generate interrupts.
See Figure 18 for an SPI pass-through timing diagram.
LSB
X
X
X
X
UP4S: UPIO4 SPI pass-through-mode enable bit. A
logic 1 maps the inverted CS signal to the UPIO4 pin.
Therefore, UPIO4 is low (near DGND) when SPI pass-
through mode is active, and is high (near DV_DD or
CPOUT) when the mode is inactive. A logic 0 disables
the UPIO4 SPI pass-through mode. The power-on
default is 0.
UP3S: UPIO3 SPI pass-through-mode enable bit. A
logic 1 maps the SCLK signal to UPIO3 (directly with no
inversion), while a logic 0 disables the UPIO3 SPI pass-
through mode. The power-on default is 0.
UP2S: UPIO2 SPI pass-through-mode enable bit. A
logic 1 maps the DIN signal to UPIO2 (directly with no
inversion), while a logic 0 disables the UPIO2 SPI pass-
through mode. The power-on default is 0.
UP1S: UPIO1 SPI pass-through-mode enable bit. A
logic 1 maps the UPIO1 input signal to DOUT (directly
with no inversion), while a logic 0 disables the UPIO1
SPI pass-through mode. The power-on default is 0.
CS
WRITE TO DAS TO ENABLE SPI MODE
WRITE THROUGH DAS TO UPIO DEVICE
NORMAL WRITE TO DAS
SCLK
DIN
D_N D_N-1 D_N-2 D_N-3 D₃ D₂ D₁ D₀ E_N E_N-1 E_N-2 E_N-3 X
XX
X D₇ D₆ D₅ D₄ D₃ D₂ D₁ D₀
DOUT
E₃ E₂ E₁ E₀
UPIO4
SET BY UPIO4_CTRL REGISTER
SET BY UPIO4_CTRL REGISTER
UPIO3
SET BY UPIO3_CTRL REGISTER
SET BY UPIO3_CTRL REGISTER
UPIO2
SET BY UPIO2_CTRL REGISTER
E_N E_N-1 E_N-2 E_N-3 X
XX
X
SET BY UPIO2_CTRL REGISTER
UPIO1
SET BY UPIO1_CTRL REGISTER
E₃ E₂ E₁ E₀
SET BY UPIO1_CTRL REGISTER
Figure 18. SPI Pass-Through Timing Diagram
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