MAX1497 Datasheet, PDF (6/33 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and μC Interface

3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and µC Interface
TIMING CHARACTERISTICS (Notes 11, 12, Figure 8)
(AV_DD = DV_DD = V_DD = +2.7V to +5.25V, GND = 0, GLED = 0, V_LED = +2.7V to +5.25V, V_REF+ - V_REF- = 2.048V (external reference)
C_REF+ = C_REF- = 0.1µF, C_VNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at T_A = T_MIN to T_MAX.
Typical values are at T_A = +25°C, unless otherwise noted.)
PARAMETER
SCLK Operating Frequency
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK Setup
DIN to SCLK Hold
CS Fall to SCLK Rise Setup
SCLK Rise to CS Rise Hold
SCLK Fall to DOUT Valid
CS Rise to DOUT Disable
CS Fall to DOUT Enable
SYMBOL
f_SCLK
t_CH
t_CL
t_DS
t_DH
t_CSS
t_CSH
t_DO
t_TR
t_DV
CONDITIONS
C_LOAD = 50pF, Figures 13, 14
C_LOAD = 50pF, Figures 13, 14
C_LOAD = 50pF, Figures 13, 14
MIN TYP MAX UNITS
0
4.2
MHz
100
ns
100
ns
50
ns
0
ns
50
ns
0
ns
120
ns
120
ns
120
ns
Note 1: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after nulling the gain error and
offset error.
Note 2: Offset calibrated. See OFFSET_CAL1 and OFFSET_CAL2 (MAX1499 only) in the On-Chip Registers section.
Note 3: Offset nulled.
Note 4: Offset drift error is eliminated by recalibration at the new temperature.
Note 5: The input voltage range for the analog inputs is given with respect to the voltage on the negative input of the differential pair.
Note 6: V_AIN+ or V_AIN- = -2.2V to +2.2V. V_REF+ or V_REF- = -2.2V to +2.2V. All input structures are identical. Production tested on
AIN+ and REF+ only.
Note 7: Measured at DC by changing the power-supply voltage from 2.7V to 5.25V and measuring the effect on the conversion
error with external reference. PSRR at 50Hz and 60Hz exceeds 120dB with filter notches at 50Hz and 60Hz (Figure 2).
Note 8: CLK and SCLK are disabled.
Note 9: LED drivers are disabled.
Note 10: Power-supply currents are measured with all digital inputs at either GND, DV_DD, or V_DD and with the device in internal-clock mode.
Note 11: All input signals are specified with t_RISE = t_FALL = 5ns (10% to 90% of DV_DD) and are timed from a voltage level of 50% of
DV_DD, unless otherwise noted.
Note 12: See the serial-interface timing diagrams.
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