MAX1497 Datasheet, PDF (10/33 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and μC Interface

3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and µC Interface
PIN
MAX1497 MAX1499
1
31
2
32
3
1
4
2
5
3
6
4
7
5
8
—
9
8
10
9
11
10
12
11
13
12
14
13
15
14
16
15
17
16
18
17
19
18
20
20
21
21
22
22
23
23
24
24
Pin Description
NAME
VNEG
REF-
REF+
AIN+
AIN-
I_SET
GND
V_DD
CLK
EOC
CS
DIN
SCLK
DOUT
DIG0
DIG1
GLED
DIG2
DIG3
SEGA
SEGB
SEGC
SEGD
SEGE
FUNCTION
-2.5V Charge-Pump Voltage-Output. Connect a 0.1µF capacitor to GND.
Negative Reference Voltage Input. For internal reference operation, connect REF- to
GND. For external reference operation, bypass REF- to GND with a 0.1µF capacitor and
set V_REF- from -2.2V to +2.2V, provided V_REF+ > V_REF-.
Positive Reference Voltage Input. For internal reference operation, connect a 4.7µF
capacitor from REF+ to GND. For external reference operation, bypass REF+ to GND
with a 0.1µF capacitor and set V_REF+ from -2.2V to +2.2V, provided V_REF+ > V_REF-.
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to GND
with a 0.1µF or greater capacitor.
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1µF or greater capacitor.
Segment Current Controller. Connect to ground through a resistor to set the segment
current. See Table 6 for segment current selection.
Ground
Analog and Digital Circuit Supply Voltage. Connect V_DD to a +2.7V to +5.25V power
supply. Bypass V_DD to GND with a 0.1µF and a 4.7µF capacitor.
External Clock Input. When the EXTCLK register bit is set to one, CLK is the master clock
input (frequency = 4.9152MHz) for the modulator and the filter. When the EXTCLK
register bit is reset to zero, the internal clock is used. Connect CLK to GND or DV_DD
(MAX1499) or V_DD (MAX1497) when the internal oscillator is used.
Active-Low End-of-Conversion Logic Output. A logic low at EOC indicates that a new
ADC result is available in the ADC result register.
Active-Low Chip Select Input. Forcing CS low activates the serial interface.
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK may idle high or low.
Serial Data Output. DOUT presets serial data in response to register queries. Data shifts
out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
Digit 0 Driver
Digit 1 Driver
Ground for LED-Display Segment Driver
Digit 2 Driver
Digit 3 Driver
Segment A Driver
Segment B Driver
Segment C Driver
Segment D Driver
Segment E Driver
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