MAX1497 Datasheet, PDF (13/33 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and μC Interface

3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and µC Interface
0
-40
-80
-120
-160
-200
0
10 20 30 40 50 60
FREQUENCY (Hz)
Figure 2. Frequency Response of the SINC⁴ Filter (Notch at 60Hz)
external-clock mode. When using the internal oscillator,
connect CLK to GND or DV_DD for the MAX1499, or con-
nect CLK to V_DD for the MAX1497. The MAX1497/
MAX1499 ideally operate with a 4.9152MHz clock to
achieve maximum rejection of 50Hz/60Hz common-
mode, power-supply, and normal-mode noise.
Internal-Clock Mode
The MAX1497/MAX1499 contain an internal oscillator.
The power-up condition for the MAX1497/MAX1499 is
internal clock operation with the EXTCLK bit in the con-
trol register equal to zero. Using the internal oscillator
saves board space by removing the need for an exter-
nal clock source.
External-Clock Mode
For external clock operation, set the EXTCLK bit in the
control register to one and drive CLK with a 4.9152MHz
clock source for best 50Hz/60Hz rejection ratio. Other
external clock frequencies allow for custom conversion
rates. A 2.4576MHz clock signal reduces the conver-
sion rate and the LED update rate by a factor of two
while keeping good 50Hz/60Hz noise rejection. The
MAX1497/MAX1499 operate with an external clock
source of up to 5.05MHz.
Charge Pump
The MAX1497/MAX1499 contain an internal charge pump
to provide the negative supply voltage for the internal
analog input/reference buffers. The bipolar input range of
the analog input/reference buffers allows this device to
accept negative inputs with high source impedances.
Connect a 0.1µF capacitor from VNEG to GND.
A
F
D
G
DIGIT 4
A
A
A
A
BF _G B F _G BF _G BF _G B
CE
CE
CE
CE
C
DP
DP
DP
DP
DP
D
D
D
D
DIGIT 3
DIGIT 2
DIGIT 1
DIGIT 0
Figure 3. Segment Connection for the MAX1499 (4.5 Digits)
A
F
D
G
DIGIT 3
A
A
A
BF _G B F _G BF _G B
CE
DP
CE
DP
D
CE
DP
D
C
DP
D
DIGIT 2
DIGIT 1
DIGIT 0
Figure 4. Segment Connection for the MAX1497 (3.5 Digits)
Table 1. LED Priority Table
SEG_SEL SPI/ADC HOLD PEAK
DISPLAY VALUES
FORM
1
X
X
X
LED segment
registers
0
1
X
X ^{LED display register}
(user written)
0
0
1
X LED display register
0
0
0
1 Peak register
0
0
0
0 ADC result register
X = Don’t care.
LED Driver
The MAX1499 has a 4.5-digit common-cathode display
driver and the MAX1497 has a 3.5-digit common-cath-
ode display driver. Figures 3 and 4 show the connection
schemes for a standard seven-segment LED display.
The LED update rate is 2.5Hz. The MAX1497/
MAX1499 automatically display the results of the ADC, if
desired (Table 1). The MAX1497/MAX1499 also allow
independent control of the LED driver through the serial
interface, allowing for data processing of the ADC result
before showing the result on the LED. Additionally, each
LED segment can be individually controlled (see the
LED segment-display register sections).
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