MAX1497 Datasheet, PDF (3/33 Pages) Maxim Integrated Products – 3.5- and 4.5-Digit, Single-Chip ADCs with LED Drivers and μC Interface

3.5- and 4.5-Digit, Single-Chip ADCs with LED
Drivers and µC Interface
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = DV_DD = V_DD = +2.7V to +5.25V, GND = 0, GLED = 0, V_LED = +2.7V to +5.25V, V_REF+ - V_REF- = 2.048V (external reference)
C_REF+ = C_REF- = 0.1µF, C_VNEG = 0.1µF. Internal clock mode, unless otherwise noted. All specifications are at T_A = T_MIN to T_MAX.
Typical values are at T_A = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
ANALOG INPUTS (AIN+, AIN-) (bypass to GND with 0.1µF or greater capacitors)
AIN Input Voltage Range (Note 5)
RANGE bit = 0
RANGE bit = 1
AIN Absolute Input Voltage
Range to GND
MIN TYP MAX UNITS
-2.0
+2.0
-0.2
+0.2
V
-2.2
+2.2
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
Internal clock mode, 50Hz and 60Hz ±2%
100
External clock mode, 50Hz and 60Hz ±2%,
f_CLK = 4.9152MHz
120
dB
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
CMR For 50Hz and 60Hz ±2%, R_SOURCE < 10kΩ
150
dB
Common-Mode Rejection
Input Leakage Current
CMR At DC
100
dB
10
nA
Input Capacitance
Average Dynamic Input Current
(Note 6)
LOW-BATTERY VOLTAGE MONITOR (LOWBATT) (MAX1499 only)
10
pF
-20
+20
nA
LOWBATT TripThreshold
2.048
V
LOWBATT Leakage Current
10
pA
Hysteresis
20
mV
INTERNAL REFERENCE (REF- = GND, INTREF bit = 1) (bypass REF+ to GND with a 4.7µF capacitor)
REF Output Voltage
REF Output Short-Circuit Current
V_REF AV_DD = V_DD = 5V
2.007 2.048 2.089
V
1
mA
REF Output Temperature
Coefficient
TC_VREF AV_DD = V_DD = 5V
40
ppm/°C
Load Regulation
I_SOURCE = 0 to 300µA, I_SINK = 0 to 30µA
6
Line Regulation
50
0.1Hz to 10Hz
25
Noise Voltage
10Hz to 10kHz
400
EXTERNAL REFERENCE (INTREF bit = 0) (bypass REF+ and REF- to GND with 0.1µF or greater capacitors)
mV/µA
µV/V
µV_P-P
REF Input Voltage
Absolute REF+, REF- Input
Voltage to GND
Differential (V_REF+ - V_REF-)
2.048
V
-2.2
+2.2
Normal-Mode 50Hz and 60Hz
Rejection (Simultaneously)
Internal clock mode, 50Hz and 60Hz ±2%
100
External clock mode, 50Hz and 60Hz ±2%,
f_CLK = 4.9152MHz
120
dB
Common-Mode 50Hz and 60Hz
Rejection (Simultaneously)
CMR For 50Hz and 60Hz ±2%, R_SOURCE < 10kΩ
150
dB
Common-Mode Rejection
Input Leakage Current
CMR At DC
100
dB
10
nA
_______________________________________________________________________________________ 3