MAX109 Datasheet, PDF (6/29 Pages) Maxim Integrated Products – 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
AC ELECTRICAL CHARACTERISTICS (continued)
(V_CCA = V_CCI = V_CCD = 5V, V_CCO = 3.3V, V_EE = -5V, GNDA = GNDI = GNDD = GNDO = GNDR = 0V, f_CLK = 2.2Gsps, analog input
amplitude at -1dBFS differential, clock input amplitude 400mV_P-P differential, digital output pins differential R_L = 100Ω. Typical values
are at T_A = +25°C, unless otherwise noted.)
PARAMETER
Spurious Free Dynamic Range
Signal-to-Noise-Plus-Distortion
Ratio
Third-Order Intermodulation
Metastability Probability
TIMING CHARACTERISTICS
Maximum Sample Rate
Clock Pulse-Width Low
Clock Pulse-Width High
Aperture Delay
Aperture Jitter
Reset Input Data Setup Time
Reset Input Data Hold Time
CLK-to-DCO Propagation Delay
SYMBOL
CONDITIONS
SFDR₃₀₀ f_IN = 300MHz, f_CLK = 2.2Gsps
SFDR₁₀₀₀ f_IN = 1000MHz, f_CLK = 2.2Gsps (Note 8)
SFDR₁₆₀₀ f_IN = 1600MHz, f_CLK = 2.2Gsps (Note 8)
SFDR₂₅₀₀ f_IN = 2500MHz, f_CLK = 2.2Gsps
SFDR₅₀₀ f_IN = 500MHz, f_CLK = 2.5Gsps
SFDR₁₆₀₀ f_IN = 1600MHz, f_CLK = 2.5Gsps
SINAD₃₀₀ f_IN = 300MHz, f_CLK = 2.2Gsps
SINAD₁₀₀₀ f_IN = 1000MHz, f_CLK = 2.2Gsps (Note 8)
SINAD₁₆₀₀ f_IN = 1600MHz, f_CLK = 2.2Gsps (Note 8)
SINAD₂₅₀₀ f_IN = 2500MHz, f_CLK = 2.2Gsps
SINAD₅₀₀ f_IN = 500MHz, f_CLK = 2.5Gsps
SINAD₁₆₀₀ f_IN = 1600MHz, f_CLK = 2.5Gsps
IM3
f_IN1 = 1590MHz, f_IN2 = 1610MHz at -7dBFS
f_CLK(MAX)
t_PWL
t_PWH
t_AD
t_AJ
t_SU
t_HD
t_PD1
t_PD1DDR
t_CLK = t_PWL + t_PWH (Note 8)
t_CLK = t_PWL + t_PWH (Note 8)
(Note 8)
(Note 8)
DCO = f_CLK / 4, CLK fall to DCO rise time
DCO = f_CLK / 8, DDR mode, CLK fall to
DCO rise time
MIN
44.4
43.7
40.4
37.9
2.2
180
180
300
250
TYP
61.7
51.1
50.3
45.0
53.7
44.6
44.1
43.1
42.1
40.1
43.1
40.5
-60
10^-14
200
0.2
1.6
1.6
MAX UNITS
dBc
dB
dBc
Gsps
ps
ps
ps
ps
ps
ps
ns
t_PD1QDR
DCO = f_CLK / 16, QDR mode, CLK fall to
DCO rise time
1.6
t_PD2
DCO = f_CLK / 4, DCO rise to data transition
(Note 8)
-520
+520
DCO-to-Data Propagation Delay
t_PD2DDR
DCO = f_CLK / 8, DDR mode, DCO rise to
data transition (Note 8)
-520 +
2t_CLK
2t_CLK
520 +
2t_CLK
ps
t_PD2QDR
DCO = f_CLK / 16, QDR mode, DCO rise to
data transition (Note 8)
-520 +
2t_CLK
2t_CLK
520 +
2t_CLK
DCO Duty Cycle
Clock mode independent
45 to
%
55
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