MAX109 Datasheet, PDF (20/29 Pages) Maxim Integrated Products – 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

8-Bit, 2.2Gsps ADC with Track/Hold Amplifier
and 1:4 Demultiplexed LVDS Outputs
CLKN
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLKP
N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
CLKP
DCON
DCOP
PORTA DATA
SAMPLE HERE
N+1
t_PD1DDR
t_PD2DDR
N+5
PORTB DATA
N+2
N+6
PORTC DATA
N+3
N+7
PORTD DATA
N
N+4
N+8
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
Figure 7. Timing Diagram for DDR Mode, fCLK / 8 Mode
CLKN
ADC SAMPLE NUMBER
ADC SAMPLES ON THE RISING EDGE OF CLKP
N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19
CLKP
DCON
DCOP
PORTA DATA
FROM DLL IN FPGA
SAMPLE HERE
N+1
t_PD1QDR
t_PD2QDR
N+5
PORTB DATA
N+2
N+6
PORTC DATA
N+3
N+7
PORTD DATA
N
N+4
N+8
NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B
PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND
PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.
Figure 8. Timing Diagram for QDR Mode, fCLK / 16 Mode
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