MAX109 Datasheet, PDF(19/29 Page) Maxim Integrated Products – 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

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MAX109 Datasheet, PDF (19/29 Pages) Maxim Integrated Products – 8-Bit, 2.2Gsps ADC with Track/Hold Amplifier and 1:4 Demultiplexed LVDS Outputs

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8-Bit, 2.2Gsps ADC with Track/Hold Amplifier

and 1:4 Demultiplexed LVDS Outputs

CLKN

ADC SAMPLE NUMBER

ADC SAMPLES ON THE RISING EDGE OF CLKP

N N + 1 N + 2 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19

CLKP

DCON

DCOP

PORTA DATA

tPWH

tPD1

tPWL

tCLK

SAMPLE HERE

N+1

tPD2

N+5

PORTB DATA

N+2

N+6

PORTC DATA

N+3

N+7

PORTD DATA

N+4

N+8

NOTE: THE LATENCY TO THE D PORT IS 7.5 CLOCK CYCLES, THE LATENCY TO THE C PORT IS 8.5 CLOCK CYCLES, THE LATENCY TO THE B

PORT IS 9.5 CLOCK CYCLES, AND THE LATENCY TO THE A PORT IS 10.5 CLOCK CYCLES. ALL DATA PORTS (PORTA, PORTB, PORTC, AND

PORTD) ARE UPDATED ON THE RISING EDGE OF THE DCOP CLOCK.

Figure 6. Timing Diagram for SDR Mode, fCLK / 4 Mode

(double data rate), and QDR (quadruple data rate).

Setting these two bits for different modes allows the

user to update and process the outputs at one-quarter

(SDR mode), one-eighth (DDR mode), or one-sixteenth

(QDR mode) the sampling clock (Table 2), relaxing the

need for an ultra-fast FPGA or data-capture interface.

Data is presented on all four ports of the converter-

demultiplexer circuit outputs. Note that there is a data

latency between the sampled data and each of the out-

put ports. The data latency is 10.5 clock cycles for

PortA, 9.5 clock cycles for PortB, 8.5 clock cycles for

PortC, and 7.5 clock cycles for PortD. This holds true for

all demultiplexer modes. Figures 6, 7, and 8 display the

demultiplexer timing for fCLK / 4, fCLK / 8, and fCLK / 16

modes.

Pseudorandom Number (PRN) Generator

The MAX109 features a PRN generator that enables the

user to test the demultiplexed digital outputs at full

clock speed and with a known test pattern. The PRN

generator is a combination of shift register and feed-

back logic with 255 states. When PRN is high, the inter-

Table 3. Pseudorandom Number

Generator Patterns

CODE

OUTPUT PRN PATTERN

00000001

00000010

00000100

00001000

00010001

00100011

01000111

10001110

00011100

00111000

250

00110100

251

01101000

252

11010000

253

10100000

254

01000000

255

10000000

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