DS80C410 Datasheet, PDF (51/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
extended stack pointer. The additional 256 Bytes of internal SRAM are used to configure and operate the 15 CAN-
controller message centers.
Extended Stack Pointer
The DS80C410 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the
performance of large programs written in high-level languages such as C. To enable the 10-bit stack pointer, set
the stack-address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit
stack located in the scratchpad RAM area. When the SA bit is set, the device addresses up to 1kB of internal
MOVX memory for stack purposes. The 10-bit stack pointer address is generated by concatenating the lower two
bits of the extended stack pointer (ESP;9Bh) and the traditional 8051 stack pointer (SP;81h).
On-Chip Arithmetic Accelerator
An on-chip math accelerator allows the microcontroller to perform 32-bit and 16-bit multiplication, division, shifting,
and normalization using dedicated hardware. Math operations are performed by sequentially loading three special
registers. The mathematical operation is determined by the sequence in which three dedicated SFRs (MA, MB, and
MCNT0) are accessed, eliminating the need for a special step to choose the operation. The normalize function
facilitates the conversion of 4-Byte unsigned binary integers into floating point format. Table 10 shows the
operations supported by the math accelerator and their time of execution.
Table 10. Arithmetic Accelerator Execution Times
OPERATION
32-Bit/16-Bit Divide
16-Bit/16-Bit Divide
16-Bit/16-Bit Multiply
32-Bit Shift Left/Right
32-Bit Normalize
RESULT
32-Bit Quotient, 16-Bit Remainder
16-Bit Quotient, 16-Bit Remainder
32-Bit Product
32-Bit Result
32-Bit Mantissa, 5-Bit Exponent
EXECUTION TIME
36 tCLCL
24 tCLCL
24 tCLCL
36 tCLCL
36 tCLCL
Table 11 demonstrates the procedure to perform mathematical operations using the hardware math accelerator.
The MA and MB registers must be loaded and read in the order shown for proper operation, although accesses to
any other registers can be performed between accesses to the MA or MB registers. An access to the MA, MB, or
MC registers out of sequence corrupt the operation, requiring the software to clear the MST bit to restart the math
accelerator state machine. See the descriptions of the MCNT0 and MCNT1 SFRs for details about how the shift
and normalize functions operate.
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