DS80C410 Datasheet, PDF (14/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS)
(V_CC3 = 3.0V to 3.6V, V_CC1 = 1.8V ±10%, T_A = -40∞C to +85∞C.) (Note 1)
PARAMETER
SYMBOL
75MHz
MIN MAX
External Crystal Frequency
VARIABLE CLOCK
MIN
MAX
4
40
UNITS
Clock Mutliplier 2X Mode
1 / tCLK
16
37.5
MHz
Clock Multiplier 4X Mode
11
18.75
External Oscillator Frequency
DC
75
Clock Mutliplier 2X Mode
1 / tCLK
16
37.5
MHz
Clock Multiplier 4X Mode
11
18.75
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
tPLPH
tPLIV
tPXIX
21.7
8.7
0
2tCLCL - 5
0
ns
2tCLCL - 18
ns
ns
Input Instruction Float After PSEN
tPXIZ
See MOVX
Characteristics
ns
Port 7 Address to Valid Instruction In
tAVIV1
21.0
3tCLCL - 19
ns
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
tAVIV2
24.7
3tCLCL + tCLCH - 22
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in
the System Clock Time Periods table.
The precalculated 75MHz min/max timing specifications assume an exact 50% duty cycle.
All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16ñA19), Port 5.4ñ5.7
(PCE0-3), Port 6.0ñ6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0ñA7).
References to the XTAL, XTAL1, or CLK signal in the timing diagrams are to assist in determining the relative occurrence of events,
not for determining absolute signal timing with respect to the external clock.
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