DS80C410 Datasheet, PDF (16/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
Note 1:
Note 2:
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Note 4:
Note 5:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL, tCLCH, tCHCL are time
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16ñA19), Port 5.4ñ5.7
(PCE0-3), Port 6.0ñ6.5 (CE4-7, A20, A2), Port 7 (demultiplexed mode A0ñA7).
References to the XTAL or CLK signal in the timing diagrams are to assist in determining the relative occurrence of events, not for
determining absolute signal timing with respect to the external clock.
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