DS80C410 Datasheet, PDF (32/102 Pages) Dallas Semiconductor – Network Microcontrollers with Ethernet and CAN

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
PIN
NAME
FUNCTION
58
A14
P2.4 A12 Program/Data Memory Address 12
P2.5 A13 Program/Data Memory Address 13
57
A15
P2.6
P2.7
A14 Program/Data Memory Address 14
A15 Program/Data Memory Address 15
20
P3.0
Port 3, I/O. Port 3 functions as an 8-bit, bidirectional I/O port, and as an alternate interface for several resources
found on the traditional 8051. The reset condition of Port 3 is all bits at logic 1 through a weak pullup. The logic
1 state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
21
P3.1
When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is
written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition
22
P3.2
driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
23
P3.3
Port
Alternate Function
24
P3.4
P3.0 RXD0 Serial Port 0 Receive
P3.1 TXD0 Serial Port 0 Transmit
25
P3.5
P3.2 INT0 External Interrupt 0
P3.3 INT1 External Interrupt 1
26
P3.6
P3.4 T0 Timer 0 External Input
P3.5 T1/CLKO Timer 1 External Input/External Clock Output
27
P3.7
P3.6
P3.7
WR External Data Memory Write Strobe
RD External Data Memory Read Strobe
Port 4, I/O. Port 4 can function as an 8-bit, bidirectional I/O port, and as the source for external address and
48
P4.0
chip-enable signals for program and data memory. Port pins are configured as I/O or memory signals through
the P4CNT register. The reset condition of Port 4 is all bits at logic 1 through a weak pullup. The logic 1 state
47
P4.1
also serves as an input mode, since external circuits writing to the port can override the weak pullup. When
software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is written
46
P4.2
to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition driver,
followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
45
P4.3
becomes the output (and input) high state.
Port
Alternate Function
44
P4.4
P4.0 CE0 Program Memory Chip Enable 0
P4.1 CE1 Program Memory Chip Enable 1
43
P4.5
P4.2 CE2 Program Memory Chip Enable 2
P4.3 CE3 Program Memory Chip Enable 3
42
P4.6
P4.4 A16 Program/Data Memory Address 16
P4.5 A17 Program/Data Memory Address 17
41
P4.7
P4.6
P4.7
A18 Program/Data Memory Address 18
A19 Program/Data Memory Address 19
35
P5.0
Port 5, I/O. Port 5 can function as an 8-bit, bidirectional I/O port, the CAN interface, Timer 3 input, and/or as
peripheral-enable signals. The reset condition of Port 5 is all bits at logic 1 through a weak pullup. The logic 1
state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
34
P5.1
When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is
written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition
33
P5.2
driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
32
P5.3
Port
Alternate Function
31
P5.4
P5.0 C0TX CAN0 Transmit Output ñ Unavailable on DS80C411
P5.1 C0RX CAN0 Receive Input ñ Unavailable on DS80C411
30
P5.5
P5.2 T3 Timer 3 External Input
P5.3 None
29
P5.6
P5.4
P5.5
PCE0 Peripheral Chip Enable 0
PCE1 Peripheral Chip Enable 1
28
P5.7
P5.6
P5.7
PCE2 Peripheral Chip Enable 2
PCE3 Peripheral Chip Enable 3
56
P6.0
Port 6, I/O. Port 6 can function as an 8-bit, bidirectional I/O port, as program and data memory address/chip-
enable signals, and/or a third serial port. The reset condition of Port 6 is all bits at logic 1 through a weak pullup.
The logic 1 state also serves as an input mode, since external circuits writing to the port can override the weak
55
P6.1
pullup. When software clears any port pin to 0, the device activates a strong pulldown that remains on until
either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong
54
P6.2
transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port
once again becomes the output (and input) high state.
53
P6.3
Port
Alternate Function
52
P6.4
P6.0 CE4 Program Memory Chip Enable 4
P6.1 CE5 Program Memory Chip Enable 5
51
P6.5
P6.2 CE6 Program Memory Chip Enable 6
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