MAX14900E Datasheet, PDF (5/31 Pages) Maxim Integrated Products – Global and Per-Channel Diagnostics

MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
Electrical Characteristics (continued)
(V_DD = 10V to 36V, V₅ = 4.5V to 5.5V, V_L = 2.5V to 5.5V, T_A = -40°C to +125°C, unless otherwise noted. Typical values are at V_DD = 24V,
V₅ = 5V, V_L = 3.3V, and T_A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SPI TIMING CHARACTERISTICS (Figure 4)
CLK Clock Period
t_CH+CL
50
ns
CLK Pulse-Width High
t_CH
5
ns
CLK Pulse-Width Low
t_CL
5
ns
FLTR = low (Note 4)
5
CS Fall-to-CLK Rise Time
t_CSS
FLTR = high
ns
300
SDI Hold Time
t_DH
5
ns
SDI Setup Time
t_DS
5
ns
Output Data Propagation Delay
t_DO
C_L = 10pF. CLK falling-edge to SDO stable
25
ns
SDO Rise and Fall Times
t_FT
C_L = 10pF
4
ns
CS Hold Time
t_CSH
(Note 4)
50
ns
FLTR = low (Note 4)
50
CS Pulse-Width High
t_CSPW
FLTR = high
ns
280
PROTECTION SPECIFICATIONS
Channel Thermal-Shutdown
Threshold
T_{C_SD}
Temperature rising
+170
°C
Thermal-Shutdown Hysteresis
Global Thermal-Shutdown
Threshold
T_{C_SD_HYS}
T_{G_SD}
Temperature rising
15
°C
150
°C
Global Thermal-Shutdown
Hysteresis
T_{G_SD_HYS}
10
°C
ESD Protection
V_ESD
O_ pins, Human Body Model (Note 6)
All other pins, Human Body Model
±15
kV
±2
Note 2: All units are production tested at T_A = +25°C. Specifications over temperature are guaranteed by design.
Note 3: All logic input pins except CS have a pulldown resistor. CS has a pullup resistor.
Note 4: Specifications are guaranteed by design; not production tested.
Note 5: Channel-to-channel skew is defined as the difference in propagation delays between channels on the same device with the
same polarity.
Note 6: Bypass V_DD pins to AGND with a 1µF capacitor as close as possible to the device for high-ESD protection.
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