MAX14900E Datasheet, PDF (4/31 Pages) Maxim Integrated Products – Global and Per-Channel Diagnostics

MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
Electrical Characteristics (continued)
(V_DD = 10V to 36V, V₅ = 4.5V to 5.5V, V_L = 2.5V to 5.5V, T_A = -40°C to +125°C, unless otherwise noted. Typical values are at V_DD = 24V,
V₅ = 5V, V_L = 3.3V, and T_A = +25°C.) (Note 2)
PARAMETER
TIMING CHARACTERISTICS
High-Side Mode LTH Output
Propagation Delay
High-Side Mode HTL Output
Propagation Delay
Push-Pull Output LTH
Propagation Delay
Push-Pull Output HTL
Propagation Delay
Output Rise and Fall Time
Output Switching Rate
Channel-to-Channel Skew
CRC Error-Detect Propagation
Delay
CRC Error-Clear Propagation
Delay
Pulse Length of Rejected Glitch
Admitted Pulse Length
Glitch Filter Propagation
Delay Time
SYMBOL
CONDITIONS
t_{PDHS_LH}
t_{PDHS_HL}
t_{PDPP_LH}
t_{PDPP_HL}
t_R, t_F
f_O
t_{PDSK_LH},
t_{PDSK_HL}
t_{PDL_}
CERR
t_{PDH_CERR}
t_GL
High-side mode, delay from IN_ transition
(parallel mode) or CS rising-edge
(serial mode) to O_ rising by 0.5V;
R_L = 48Ω, C_L = 1nF, t_R/t_F ≤ 20ns,
FLTR = low, Figure 1 (Note 4)
High-side mode, delay from IN_ transition
(parallel mode) or CS rising-edge
(serial mode) to O_ falling by 0.5V,
R_L = 48Ω, C_L = 1nF, t_R/t_F ≤ 20ns,
FLTR = low, Figure 1 (Note 4)
Push-pull mode, delay from IN_ transition
(parallel mode) or CS rising-edge
(serial mode) to O_ settling to within
0.8 x V_DD, R_L = 5kΩ, C_L = 1nF,
FLTR = low, Figure 2
Push-pull mode, delay from IN_ transition
(parallel mode) or CS rising-edge
(serial mode) to O_ settling to within
0.2 x V_DD, R_L = 5kΩ, C_L = 1nF,
FLTR = low, Figure 2
High-side mode, 20% to 80%, R_L = 48Ω,
C_L = 1nF, Figure 1
Push-pull mode, 20% to 80%, R_L = 5kΩ,
C_L = 1nF, Figure 2
Push-pull mode, 20% to 80%, R_L = 240Ω,
V_CC = 24V, C_L = 1nF, Figure 2
Push-pull mode, R_L = 5kΩ or I_L = 100mA
to ground, C_L = 1nF, SRIAL = low
Push-pull mode, Figure 2 (Note 5)
Error detected on SDI data, from CS
rising-edge to CERR/IN4 falling-edge;
I_SOURCE = 5mA, Figure 3
Error cleared, from CS rising-edge to
CERR/IN4 rising, I_SOURCE = 5mA,
Figure 3
FLTR = high
FLTR = high
t_PDGF
FLTR = high
MIN
-100
0
300
TYP MAX UNITS
0.2
1
µs
0.9
2
µs
0.3
0.7
µs
0.3
0.8
µs
1.5
4
0.1
0.4
µs
0.1
0.4
100
kHz
+100
ns
14.5
30
ns
17
40
ns
80
ns
ns
140 300
ns
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