MAX14900E Datasheet, PDF (12/31 Pages) Maxim Integrated Products – Global and Per-Channel Diagnostics

MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
Pin Description (continued)
PIN
NAME
FUNCTION
CRC Error Detection Output/IN4 Input. In serial mode (SRIAL = high) with error checking enabled
9
CERR/IN4
(CRC/IN3 = high), CERR/IN4 is an active-low open-drain output that asserts when a CRC error is detected
on SDI data. In parallel mode (SRIAL = low), CERR/IN4 sets the O4 output on/off in high-side mode or
high/low in push-pull mode. CERR/IN4 has an internal 200kΩ pulldown resistor when SRIAL = 0.
CRC Enable Input/IN3 Input. In serial mode (SRIAL = high), drive CRC/IN3 high to enable CRC
10
CRC/IN3 generation/error detection on SPI data. In parallel mode (SRIAL = low), CRC/IN3 sets the O3 output
on/off in high-side mode or high/low in push-pull mode. CRC/IN3 has an internal 200kΩ pulldown resistor.
11
IN2
IN2 Input. In parallel mode (SRIAL = low), IN2 sets the O2 output on/off in high-side mode or high/low in
push-pull mode. IN2 has an internal 200kΩ pulldown resistor.
Open-Load Enable Input/IN1 Input. In serial mode (SRIAL = high), drive OL/IN1 high to enable open-load
detection on all eight O_ outputs that are configured in high-side mode, overriding the serial configuration.
12
OL/IN1 Drive OL/IN1 low to disable open-load detection unless enabled by the serial interface. In parallel mode
(SRIAL = low), OL/IN1 sets the O1 output on/off in high-side mode or high/low in push-pull mode. OL/IN1
has a 200kΩ pulldown resistor that is always connected.
13
V_L
Logic Supply Input. V_L defines the logic levels on all I/O logic interface pins from 2.5V to 5.5V.
Bypass V_L to AGND with a 0.1µF ceramic capacitor as close as possible to the device.
14, 18,
19, 23,
38, 42,
43, 47
V_DD
Supply Voltage Input. V_DD supply is 10V to 36V. Bypass the V_DD pins to a ground plane with a 1µF
ceramic capacitor. Externally connect all V_DD pins and ensure that the maximum trace resistance
between each V_DD pin is less than 10mΩ.
15
16, 21,
40, 45
17
20
22
O1
PGND
O2
O3
O4
Driver Output 1. May be configured as a high-side switch or push-pull output.
Power Ground. Connect PGND to the ground plane.
Driver Output 2. May be configured as a high-side switch or push-pull output.
Driver Output 3. May be configured as a high-side switch or push-pull output.
Driver Output 4. May be configured as a high-side switch or push-pull output.
Global Push-Pull/High-Side Select Input. In parallel mode (SRIAL = low), drive PUSHPL high to globally
24
PUSHPL
configure all O_ outputs to operate in push-pull mode, overriding the serial configuration. Drive PUSHPL
low to configure all O_ outputs to operate in high-side mode unless configured as push-pull by the serial
interface. PUSHPL has an internal 200kΩ pulldown resistor.
25–27,
33–36
28
29
30
31
32
N.C.
FLTR
AGND
V₅
EN
REXT
No Connection. Not internally connected.
Glitch Filter Enable Input. Set FLTR high to enable glitch filtering on every logic input except SDI and CLK.
FLTR has an internal 200kΩ pulldown resistor.
Analog Ground. Connect AGND to the ground plane.
5V Supply Input. Bypass V₅ to AGND with a 1µF ceramic capacitor as close as possible to the device.
Enable Input. Drive EN high to enable normal operation for all O_ outputs. Drive EN low to force all
O_ outputs into high-impedance mode. EN has an internal 200kΩ pulldown resistor.
External Resistor Connection. Connect a 56kΩ ±1% resistor from REXT to AGND.
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