MAX14900E Datasheet, PDF (21/31 Pages) Maxim Integrated Products – Global and Per-Channel Diagnostics

MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
previous SDI data reception. Note that ERR is delayed
by one SPI cycle, i.e., it indicates that a CRC error was
detected in the previous SPI data cycle. The CERR/IN4
output is immediately set active when a CRC error is
detected, allowing the controller to resend the last SDI
data or take other action.
The CRO_ bits are the CRC bits that the MAX14900E
calculates on the 8-/16-bit diagnostics and/or status data
plus the ERR bit i.e., the output FCS is calculated on
9/17 bits. This allows the controller to detect errors on the
SDO data received from the MAX14900E.
Applications Information
Driving Inductive Loads
In high-side mode, when the high-side switch turns off, an
inductive load will cause the O_ voltage to swing negative
in order to continue sourcing the load’s inductive current
while the inductor field collapses. The internal diodes sup-
port turn-off of inductive loads of up to 1.5H and currents
of up to 1.9A.
Driving Lamp Loads
Lamp loads are incandescent lamps where the filament
resistance is strongly dependent on the filament’s tem-
perature. The initial startup current is high because a cold
filament has a very low resistance. The MAX14900E will
reliably turn on 15W lamps over the operating tempera-
ture range.
Driving Capacitive Loads
When charging/discharging purely capacitive loads with a
push-pull driver, the driver dissipates power that is propor-
tional to switching frequency. The power can be estimated
by P_D ~ C x V_DD2 x f, where C is the load capacitance,
V_DD is the supply voltage, and f is the switching fre-
quency. For example, in an application with a 1nF load
and 100kHz switching frequency, each driver dissipates
130mW at V_DD = 36V. When driving purely capacitive
loads consider a maximum capacitance of around 10nF.
Multiple SPI Devices on Shared Bus
The SDO output is high impedance when CS is logic-
high to allow connecting multiple devices in parallel on a
shared SPI bus with the SDO lines connected together.
When SDO is high impedance, an internal 200kΩ pull-
down resistor is enabled to pull SDO to GND weakly.
Paralleling of Outputs
In high-side mode, multiple outputs can be connected
together in parallel to achieve higher load currents. The
total load current should be shared equally between
these high-side switches that are operated in parallel.
This is achieved by having identical trace resistances for
all the PCB tracks from the O_ pins to the common star
connection point. This is particularly important, since the
on-resistance of each high-side switch is low: 85mΩ (typ).
Board Layout
High-speed switches require proper layout and design
procedures for optimum performance. Ensure that power-
supply bypass capacitors are placed as close as possible
to the device. Connect all V_DD pins to a V_DD plane.
Ensure that all V_DD pins have no more than 10mΩ
between them. In this case a 1µF capacitor should be
placed to the ground plane as close to the V_DD pins as
possible. In the case low resistance paths are not pos-
sible between the V_DD pins, bypass each pin to GND via
a 100nF capacitor.
A suppressor/TVS diode should be used between V_DD
and GND to clamp high-surge transients on the V_DD sup-
ply input and surges from the O_ outputs. The standoff
voltage should be higher than the maximum operating
voltage of the equipment while the breakdown voltage
should be around 40V.
As long field supply cables can generate large voltage
transients on the V_DD supply due to large di/dt, it is rec-
ommended to add a large capacitor on V_DD at the point
of field supply entry. Capacitance should be as large as
possible, but 47µF electrolytic capacitor is recommended
as a minimum.
High ESD Protection
Electrostatic discharge (ESD)-protection structures are
incorporated on all pins to protect against electrostatic
discharges up to ±2kV Human Body Model (HBM)
encountered during handling and assembly.
All O_ outputs are further protected against ESD up to
±15kV (HBM) without damage, when the part is operative
in the application circuit with a 1µF bypass capacitor on
V_DD and a suppressor/TVS diode.
In order to achieve even higher ESD levels, connect
external diodes from each output to GND and to V_DD as
described in the Surge Protection section.
Surge Protection
The MAX14900E O_ pin is tolerant to ±600V/(42Ω +
0.5µF) 1.2µs/50µs surge testing, when only using a TVS
diode on V_DD and without protection diodes on the O_
pins. It achieved over ±1.5kV/(42Ω + 0.5µF) IEC61000-
4-5 surge testing when using the Typical Operating
Circuit. The silicon diodes on O_ must have low forward
voltage diodes that support the surge currents, like
MURA205T3G. A surge-suppressor diode on the V_DD
supply must have low output impedance at the high surge
currents. The SM30TY is suitable for this. Place all diodes
and the V_DD capacitor as close to the MAX14900E pins
as possible.
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