MAX14900E Datasheet, PDF (20/31 Pages) Maxim Integrated Products – Global and Per-Channel Diagnostics

MAX14900E
Octal, High-Speed, Industrial, High-Side Switch
16-Bit Serial Configuration
Open-load detection is only available for outputs con-
figured in high-side mode. If PUSHPL = high, then all
outputs are configured as push-pull mode regardless of
the C_ bits. In serial modes, if OL/IN1 = high, then all out-
puts that are configured as high side will have open-load
detect on, regardless of the C1_ bits.
8-Bit Serial Diagnostics
If a driver is configured in push-pull mode, then a fault
means that an overload or a thermal shutdown is pres-
ent on that channel. If the driver is configured in high-
side mode, then a fault means that an overtemperature
condition is detected. If open-load detection is enabled
in high-side mode, then the F_ bit is set when either an
open-load (only possible with the high-side switch off) or
an overtemperature is detected. In a UVLO condition,
eight F_ bits are logic one.
16-Bit Serial Diagnostics
Logic-level status (S_bits) detection is only valid when no
fault is present. Each S_ bit in normal (no fault) operating
condition reports whether or not the O_ voltage is above
(= 1) or below (= 0) 7V (typ).
When all F_ and S_ bits are logic one, a UVLO condition
is present.
Table 6. 16-Bit Serial Configuration
Truth Table
C1_ C0_
0
0
0
1
1
0
1
1
O_ CONFIGURATION
High-side mode, open-load detect off
Push-pull mode
High-side mode, open-load detect on
Push-pull mode
Table 7. 8-Bit Diagnostics Truth Table
F_
O_ CONDITION
0
No fault present
1
Fault (overload, open load, or UVLO) present
Table 8. 16-Bit Serial Diagnostics
Truth Table
F_ S_
00
01
10
11
O_ STATUS
No fault detected, logic state of O_ is low
No fault detected, logic state of O_ is high
Fault detected, logic state not defined
UVLO detected
CRC Error Checking on Serial Interface
In serial mode (SRIAL = high), CRC error detection can
be enabled by setting CRC/IN3 high to minimize incorrect
operation due to noise on the SDI/SDO/CLK signals. With
CRC error detection enabled, the MAX14900E detects
errors on the SDI data that it receives from the controller
and it calculates a CRC on the SDO data that it sends to
the controller and appends this check byte to the SDO
data.
This ensures that both the SPI data sent and received
by the MAX14900E has a low likelihood of undetected
errors.
The check byte appended to all 8-bit/16-bit SDO data by
the MAX14900E contains a 7-bit frame check sequence
(FCS). This FCS is based on the CRC generator polyno-
mial x⁷ + x⁵ + x⁴ + x² + x + 1. The CRC initialization condi-
tion is 0x7F. The MAX14900E in turn expects a check byte
appended to all 8-/16-bit SDI data that it receives contain-
ing a FCS based on the same polynomial (Figure 11).
The controller should calculate the 7 FCS bits (CRI_) on
the 8-/16-bit data including the logic 1 in the first position
of the check byte. Thus the CRC is calculated on 9 or 17
bits. CRI1 is the LSB of the FCS. The MAX14900E veri-
fies this received CRC. If the MAX14900E detects CRC
errors on the received SDI data, then it ignores this data
and does not change its configuration and/or output set-
ting. Instead, the CERR/IN4 output is asserted and the
ERR bit is set in the check byte that it appends to the
8-/16-bit SDO diagnostic/status data that it sends back to
the controller during the following serial communication
cycle (Figure 12).
ERR is the error feedback bit that is sent back to the
controller to signal that a CRC error was detected on the
CS
CLK
SDI
1 CRI7 CRI6 CRI5 CRI4 CRI3 CRI2 CRI1
Figure 11. CRC Check Byte Expected From Controller
CS
CLK
SDO
ERR CRO7 CRO6 CRO5 CRO4 CRO3 CRO2 CRO1 ^Hi-Z
Figure 12. CRC Check Byte Sent by MAX14900E
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