MAX16047A Datasheet, PDF (44/61 Pages) Maxim Integrated Products – 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers

12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
I²C/SMBus-Compatible
Serial Interface
The MAX16047A/MAX16049A feature an I²C/SMBus-
compatible 2-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA and
SCL facilitate bidirectional communication between the
MAX16047A/MAX16049A and the master device at
clock rates up to 400kHz. Figure 1 shows the 2-wire
interface timing diagram. The MAX16047A/MAX16049A
are transmit/receive slave-only devices, relying upon a
master device to generate a clock signal. The master
device (typically a µC) initiates a data transfer on the
bus and generates SCL to permit that transfer.
A master device communicates to the MAX16047A/
MAX16049A by transmitting the proper address followed
by command and/or data words. The slave address
input, A0, is capable of detecting four different states,
allowing multiple identical devices to share the same seri-
al bus. The slave address is described further in the
Slave Address section. Each transmit sequence is framed
by a START (S) or REPEATED START (SR) condition and
a STOP (P) condition. Each word transmitted over the bus
is 8 bits long and is always followed by an acknowledge
pulse. SCL is a logic input, while SDA is an open-drain
input/output. SCL and SDA both require external pullup
resistors to generate the logic-high voltage. Use 4.7kΩ for
most applications.
Bit Transfer
Each clock pulse transfers one data bit. The data on
SDA must remain stable while SCL is high (Figure 9);
otherwise the MAX16047A/MAX16049A registers a
START or STOP condition (Figure 10) from the master.
SDA and SCL idle high when the bus is not busy.
START and STOP Conditions
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmis-
sion with a START condition by transitioning SDA from
high to low while SCL is high. The master device issues
a STOP condition by transitioning SDA from low to high
while SCL is high. A STOP condition frees the bus for
another transmission. The bus remains active if a
REPEATED START condition is generated, such as in
the block read protocol (see Figure 1).
Early STOP Conditions
The MAX16047A/MAX16049A recognize a STOP condi-
tion at any point during transmission except if a STOP
condition occurs in the same high pulse as a START
condition. This condition is not a legal I²C format; at least
one clock pulse must separate any START and STOP
condition.
REPEATED START Conditions
A REPEATED START may be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START condi-
tions are functionally identical.
SDA
SDA
SCL
DATA LINE STABLE, CHANGE OF
DATA VALID DATA ALLOWED
Figure 9. Bit Transfer
SCL S
START
CONDITION
Figure 10. START and STOP Conditions
P
STOP
CONDITION
44 ______________________________________________________________________________________