MAX1462 Datasheet, PDF (4/16 Pages) Maxim Integrated Products – Low-Voltage, Low-Power, 16-Bit Smart ADC

Low-Voltage, Low-Power,
16-Bit Smart ADC
Pin Description
PIN
1, 2, 12,
13, 18, 19,
31, 32, 36,
41–45
3
4
5
6
7
8
9
10
11
14, 37, 38
15
16, 17
20
21
22
23
24
25
26
NAME
N.C.
AGND
START
I.C.
D6
D7
D8
D9
D10
D11
V_DD
V_SS
CS1,
CS2
SDIO
SDO
RESET
EOC
D0
D1
D2
FUNCTION
No Connection. Not internally connected.
Analog Ground. Connect to V_DD and V_SS using 10kΩ resistors (see Functional Diagram).
Optional conversion start input signal, used for extending sensor warm-up time. Internally pulled to
V_DD with a 1MΩ (typ) resistor.
Internally Connected. Leave unconnected.
Parallel Digital Output - Bit 6
Parallel Digital Output - Bit 7
Parallel Digital Output - Bit 8
Parallel Digital Output - Bit 9
Parallel Digital Output - Bit 10
Parallel Digital Output - Bit 11 (MSB)
Positive Supply Voltage Input. Connect a 0.1µF bypass capacitor from V_DD to V_SS. Pins 14, 37, and 38
must all be connected to the positive power supply on the PC board.
Negative Supply Input
Chip-Select Input. The MAX1462 is selected when CS1 and CS2 are both high. When either CS1 or
CS2 is low, all digital outputs are high impedance and all digital inputs are ignored. CS1 and CS2 are
internally pulled high to V_DD with a 1MΩ (typ) resistor.
Serial Data Input/Output. Used only during programming/testing, when the TEST pin is high. The test
system sends commands to the MAX1462 through SDIO. The MAX1462 returns the current instruction
ROM address and data being executed by the DSP to the test system. SDIO is internally pulled to V_SS
with a 1MΩ (typ) resistor. SDIO goes high impedance when either CS1 or CS2 is low and remains in
this state until the test system initiates conversion.
Serial Data Output. Used only during programming/testing. SDO allows the test system to monitor the
DSP registers. The MAX1462 returns to the test system results of the DSP current instruction. SDO is
high impedance when TEST is low.
Reset Input. When TEST is high, a low-to-high transition on RESET enables the MAX1462 to accept
commands from the test system. This input is ignored when TEST is low. Internally pulled high to V_DD
with a 1MΩ (typ) resistor.
End of Conversion Output. A high-to-low transition of the EOC pulse can be used to latch the Parallel
Digital Output (pins D[11...0]).
Parallel Digital Output - Bit 0 (LSB)
Parallel Digital Output - Bit 1
Parallel Digital Output - Bit 2
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