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MAX11312 Datasheet, PDF (38/54 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO | |||
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MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Interrupt Mask Register (Read/Write)
BIT
FIELD NAME
DESCRIPTION
ADC flag interrupt mask
⢠Masks ADCFLAG interrupt bit when asserted.
⢠In ADC continuous-sweep mode, INT is asserted for 100nS at the end of each sweep
0
ADCFLAGMSK
whether ADCFLAG interrupt is cleared or not.
⢠1: Prevents the assertion of ADCFLAG interrupt bit from pulling INT low.
⢠0: Allows the assertion of ADCFLAG interrupt bit to pull INT low.
1
2
3
4
5
8:6
11:9
14:12
15
ADCDRMSK
ADCDMMSK
GPIDRMSK
GPIDMMSK
DACOIMSK
TMPINTMSK[2:0]
TMPEXT1MSK[2:0]
TMPEXT2MSK[2:0]
VMONMSK
ADC data ready interrupt mask
⢠Masks ADCDR interrupt bit when asserted.
⢠1: Prevents the assertion of ADCDR interrupt bit from pulling INT low.
⢠0: Allows the assertion of ADCDR interrupt bit to pull INT low.
ADC data missed interrupt mask
⢠Masks ADCDM interrupt bit when asserted.
⢠1: Prevents the assertion of ADCDM interrupt bit from pulling INT low.
⢠0: Allows the assertion of ADCDM interrupt bit to pull INT low.
GPI event ready interrupt
⢠Masks GPIDR interrupt bit when asserted.
⢠Supersedes the settings in the GPI IRQ Mode registers.
⢠1: Prevents the assertion of GPIDR interrupt bit from pulling INT low.
⢠0: Allows the assertion of GPIDR interrupt bit to pull INT low.
GPI event missed interrupt mask
⢠Masks GPIDM interrupt bit when asserted.
⢠Can be deasserted only if GPIDRMSK is deasserted.
⢠1: Prevents the assertion of GPIDM interrupt bit from pulling INT low.
⢠0: Allows the assertion of GPIDM interrupt bit to pull INT low.
DAC driver overcurrent interrupt mask
⢠Masks DACOI interrupt bit when asserted.
⢠1: Prevents the assertion of DACOI interrupt bit from pulling INT low.
⢠0: Allows the assertion of DACOI interrupt bit to pull INT low.
Internal temperature interrupt mask
⢠Masks TMPINT[2:0] interrupt bits when asserted on a bit-by-bit basis.
⢠1: Prevents the assertion of TMPINT[i] interrupt bit from pulling INT low (0â¤iâ¤2).
⢠0: Allows the assertion of TMPINT[i] interrupt bit to pull INT low (0â¤iâ¤2).
1st external temperature interrupt mask
⢠Masks TMPEXT1[2:0] interrupt bits when asserted on a bit-by-bit basis.
⢠1: Prevents the assertion of TMPEXT1[i] interrupt bit from pulling INT low (0â¤iâ¤2).
⢠0: Allows the assertion of TMPEXT1[i] interrupt bit to pull INT low (0â¤iâ¤2).
2nd external temperature interrupt mask
⢠Masks TMPEXT2[2:0] interrupt bits when asserted on a bit-by-bit basis.
⢠1: Prevents the assertion of TMPEXT2[i] interrupt bit from pulling INT low (0â¤iâ¤2).
⢠0: Allows the assertion of TMPEXT2[i] interrupt bit to pull INT low (0â¤iâ¤2).
High-voltage supply monitor mask
⢠Masks VMON interrupt bit when asserted.
⢠1: Prevents the assertion of VMON interrupt bit from pulling INT low.
⢠0: Allows the assertion of VMON interrupt bit to pull INT low.
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