MAX11312 Datasheet, PDF (24/54 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
SERIAL
INTERFACE
I²C
DAC_REF
INTERNAL OR EXTERNAL
FOR ALL PORTS
DIGITAL
CORE
DAC
SEQUENCER
CNVT
SCALING
BLOCK
PORT
ADC_INT_REF DAC_REF
REFERENCE
MUX
ADC
SCALING
BLOCK
SEQUENCER
Figure 6. DAC Configuration with ADC Monitoring
The unidirectional path configuration allows for the
transmission of signals received on a GPI-configured port
to one or more GPO-configured ports.
Pairs of adjacent PIXI ports can also form bidirectional
level translator paths that are targeted to operate with
open-drain drivers (Figure 10). In this configuration,
adjacent PIXI ports must be from the same six-channel
group: PORT0 to PORT5 or PORT6 to PORT11. When
used as a bidirectional level translator, the pair of PIXI
ports must be accompanied with external pullup resistors
to meet proper logic levels.
Internally or Externally Controlled
Analog Switch Operation
Two adjacent PIXI ports from the same group of ports (PORT0
to PORT5 or PORT6 to PORT11) can form a 60Ω analog
switch that is controlled by two different configurations. Analog
switches cannot be configured between programmable ports
in different groups, such as between PORT5 and PORT6
or between PORT0 and PORT11. In one configuration, the
switch is dynamically controlled by any other GPI-configured
PIXI port, as illustrated in Figure 11. The signal applied to that
GPI-configured port can be inverted.
In the other configuration, the switch is programmed to be
permanently “ON” by configuring the corresponding PIXI
port. To turn the switch “OFF”, the host must set that PIXI
port in high-impedance configuration.
INT
Power-Supply Brownout Detection
The MAX11312 features a brownout detection circuit that
monitors AVDDIO and AVDD pins. When AVDDIO goes
below approximately 4.0V, an interrupt is registered, and
the interrupt port is asserted if not masked. When AVDD
goes below approximately 4.0V, the device resets.
I²C Operations
The MAX11312 serial interface is compatible with the I²C
Fast Mode (SCL at 400kHz).
The MAX11312 has a configurable 7-bit slave address.
The first four bits of all MAX11312 slave addresses are
always 0111. Slave address bits A2, A1, and A0 are
shown in Table 1. The AD0 and AD1 inputs are connected
to any of three signals: DGND, DVDD, SDA, or SCL giving
eight possible slave addresses, and allowing up to eight
MAX11312 devices to share the bus.
Basic write and read transactions are structured as shown
in Table 2 and Table 3, respectively. For write transactions,
the targeted register content is modified only after the
third byte has been fully received. A burst transaction
would simply be the extension of the single register transaction,
where the address is automatically incremented from one
data word to the next (Table 4 and Table 5). Each time a
new data sample is read or written, the register address
is incremented by one until it reaches the last register
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