MAX11312 Datasheet, PDF (22/54 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
DAC Operations
The MAX11312 uses a 12-bit DAC, which operates at the
rate of 40µs per port. Since up to 12 ports can be configured
in DAC-related modes, the minimum refresh rate per port
is 2.083KHz.
No external component is required to set the offset and
gain of the DAC drivers. The PIXI port driver features a
wide output voltage range of ±10V and high-current capability
with dedicated power supplies (AVDDIO, AVSSIO).
The DAC uses either the internal or external voltage
reference. Unlike the ADC, the DAC voltage reference
cannot be configured on a port-by-port basis. DAC mode
configuration is illustrated in Figure 5.
DAC operations can be monitored by the ADC. In such a
mode, the ADC samples the DAC-configured port to allow
the host to monitor that the voltage at the port is within
expectations given the accuracy of the ADC and DAC.
This ADC monitoring mode is shown in Figure 6.
By default, the DAC updates the DAC-configured ports
sequentially. However, users can configure the DAC so
that its sequence can jump to update the port that just
received new data to convert. After having updated this
port, the DAC continues its default sequence from that
port. In that mode, users should allow a minimum of 80µs
between DAC data register updates for subsequent jump
operations.
In addition to port-specific DAC data registers, the host
can also use the same data for all DAC-related ports
using one of two preset DAC data registers.
All DAC output drivers are protected by overcurrent limit
circuitry. In case of overcurrent, the MAX11312 generates
an interrupt. Detailed status registers are offered to the
host to determine which ports are current limited.
PORT
SCALING
BLOCK
SEQUENCER
Figure 2. ADC with Single-Ended Input
ADC_INT_REF
ADC
DIGITAL
CORE
12 BITS
UP TO 400ksps
CNVT
I²C
SERIAL
INTERFACE
INT
ANY
PORT
ANY OTHER
PORT
SCALING
BLOCK
SCALING
BLOCK
Figure 3. ADC with Differential Inputs
ADC_INT_REF
SEQUENCER
ADC
DIGITAL
CORE
12 BITS
UP TO 400ksps
CNVT
I²C
SERIAL
INTERFACE
INT
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