MAX11312 Datasheet, PDF (28/54 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11312
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
two bytes. This scheme goes on until the host produces a
NACK (read transactions) or a STOP (write transactions).
There are two address incrementing modes. In one mode,
the address is simply incremented by one (default mode),
while in the other, the address is incremented contextually.
When writing DAC data registers in a burst fashion using
contextual addressing, the host would write the address
of the first port that is DAC-configured (starting from the
lowest port index). As long as the host does not issue a
STOP and another two bytes are received, the next DAC-
configured port is written. This scheme continues until the
last DAC-configured port is reached. At that point, any
additional serial clock cycle results in looping back to the
first DAC-configured port.
The contextual addressing scheme is only valid for writing
DAC data registers, as described above, and reading
ADC data registers.
Interrupt Operations
The device issues interrupts to alert the host of various
events. All events are recorded by the interrupt register.
The assertion of an interrupt register bit results in the
assertion of the interrupt port (INT) if that interrupt bit is
ANY
PORT
SERIAL
INTERFACE
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
SEQUENCER
DAC
GPI
DIGITAL
CORE
DAC
SEQUENCER
I²C
SCALING
BLOCK
GPO
ANY OTHER
PORT
INT
Figure 9. Unidirectional Level Translator Path Mode
CHIP1 WITH VDD1
LOGIC LEVEL
LOGIC
CONTROLLER
VDD1
VDD2
MAX11312
PORT[i] PORT[i+1]
CHIP2 WITH VDD2
LOGIC LEVEL
LOGIC
CONTROLLER
Figure 10. Bidirectional Level Translation Application Diagram
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