MAX1535A Datasheet, PDF (37/39 Pages) Maxim Integrated Products – Highly Integrated Level 2 SMBus Battery Charger

Highly Integrated Level 2 SMBus
Battery Charger
Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
• Minimize the current-sense resistor trace lengths,
and ensure accurate current sensing with Kelvin
connections.
• Minimize ground trace lengths in the high-current
paths.
• Minimize other trace lengths in the high-current
paths.
• Use >5mm wide traces in the high-current paths.
• Connect C1 and C2 to the high-side MOSFET
(10mm, max length).
• Minimize the LX node (MOSFETs, rectifier cathode,
inductor (15mm, max length)).
Ideally, surface-mount power components are flush
against each other with their ground terminals
almost touching. These high-current grounds are
then connected to each other with a wide, filled zone
of top-layer copper, so they do not go through vias.
The resulting top-layer subground plane is connect-
ed to the normal inner-layer ground plane at the out-
put ground terminals, which ensures that the IC’s
analog ground is sensing at the supply’s output ter-
minals without interference from IR drops and
ground noise. Other high-current paths should also
be minimized, but focusing primarily on short
ground and current-sense connections eliminates
about 90% of all PC board layout problems.
2) Place the IC and signal components. Keep the main
switching node (LX node) away from sensitive analog
components (current-sense traces and the REF
capacitor). Important: The IC must be no further than
10mm from the current-sense resistors. Quiet con-
nections to REF, VMAX, IMAX, CCV, CCI, CCS, ACIN,
and DCIN should be returned to a separate ground
(GND) island. The appropriate traces are marked on
the schematic with the ground symbol. There is very
little current flowing in these traces, so the ground
island need not be very large. When placed on an
inner layer, a sizable ground island can help simplify
the layout because the low-current connections can
be made through vias. The ground pad on the back-
side of the package should also be connected to
this quiet ground island.
3) Keep the gate drive traces (DHI and DLO) as short
as possible (L < 20mm), and route them away from
the current-sense lines and REF. These traces
should also be relatively wide (W > 1.25mm).
4) Place ceramic bypass capacitors close to the IC.
The bulk capacitors can be placed further away.
Place the current-sense input filter capacitors under
the part, connected directly to the GND pin.
5) Use a single-point star ground placed directly below
the part at the PGND pin. Connect the power ground
(ground plane) and the quiet ground island at this
location. See Figure 18 for a layout example.
Chip Information
TRANSISTOR COUNT: 11,900
PROCESS: BiCMOS
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