MAX1535A Datasheet, PDF (32/39 Pages) Maxim Integrated Products – Highly Integrated Level 2 SMBus Battery Charger

Highly Integrated Level 2 SMBus
Battery Charger
100
80
60
40
20
0
-20
-40
0.1
0
MAG
PHASE
-45
10
1k
100k
FREQUENCY (Hz)
-90
10M
CLS
GMS
ADAPTER
INPUT
CSSP
CSS
RS1
CSSN
CCS
C_CS
R_OGMS
GM_IN
SYSTEM
LOAD
Figure 13. CCI Loop Response
Figure 14. CCS Loop Diagram
from DLOV to ground and has a typical impedance of
1Ω sinking and 4Ω sourcing. This helps prevent DLO
from being pulled up when the high-side switch turns
on due to capacitive coupling from the drain to the gate
of the low-side MOSFET. This places some restrictions
on the MOSFETs that can be used. Using a low-side
MOSFET with smaller gate-to-drain capacitance can
prevent these problems.
Design Procedure
Table 12 lists the recommended components and
refers to the circuit of Figure 1. The following sections
describe how to select these components.
MOSFET Selection
MOSFETs P2 and P3 (Figure 1) provide power to the
system load when the AC adapter is inserted. These
devices may have modest switching speeds, but must
be able to deliver the maximum input current as set by
R1. As always, care should be taken not to exceed the
device’s maximum voltage ratings at the maximum
operating temperature.
The P-channel/N-channel MOSFETs (P1, N1) are the
switching devices for the step-down regulator. The
guidelines for these devices focus on the challenge of
obtaining high load-current capability when using high-
voltage (>20V) AC adapters. Low-current applications
usually require less attention. The high-side MOSFET
(P1) must be able to dissipate the resistive losses plus
the switching losses at both V_DCIN(MIN) and
V_DCIN(MAX). Calculate both these sums.
100
80
60
40
20
0
-20
-40
0.1
0
MAG
PHASE
-45
10
1k
100k
FREQUENCY (Hz)
-90
10M
Figure 15. CCS Loop Response
Ideally, the losses at V_DCIN(MIN) should be roughly
equal to losses at V_DCIN(MAX), with lower losses in
between. If the losses at V_DCIN(MIN) are significantly
higher than the losses at V_DCIN(MAX), consider increas-
ing the size of P1. Conversely, if the losses at
V_DCIN(MAX) are significantly higher than the losses at
V_IN(MIN), consider reducing the size of P1. If DCIN
does not vary over a wide range, the minimum power
dissipation occurs where the resistive losses equal the
switching losses. Choose a low-side MOSFET that has
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